static int starfive_probe()

in pinctrl-starfive.c [1215:1335]

• 98 lines of code
• 22 McCabe index (conditional complexity)

static int starfive_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct starfive_pinctrl *sfp;
	struct reset_control *rst;
	struct clk *clk;
	u32 value;
	int ret;

	sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
	if (!sfp)
		return -ENOMEM;

	sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
	if (IS_ERR(sfp->base))
		return PTR_ERR(sfp->base);

	sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
	if (IS_ERR(sfp->padctl))
		return PTR_ERR(sfp->padctl);

	clk = devm_clk_get(dev, NULL);
	if (IS_ERR(clk))
		return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");

	rst = devm_reset_control_get_exclusive(dev, NULL);
	if (IS_ERR(rst))
		return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");

	ret = clk_prepare_enable(clk);
	if (ret)
		return dev_err_probe(dev, ret, "could not enable clock\n");

	ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
	if (ret)
		return ret;

	/*
	 * We don't want to assert reset and risk undoing pin muxing for the
	 * early boot serial console, but let's make sure the reset line is
	 * deasserted in case someone runs a really minimal bootloader.
	 */
	ret = reset_control_deassert(rst);
	if (ret)
		return dev_err_probe(dev, ret, "could not deassert reset\n");

	platform_set_drvdata(pdev, sfp);
	sfp->gc.parent = dev;
	raw_spin_lock_init(&sfp->lock);

	ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
	if (ret)
		return dev_err_probe(dev, ret, "could not register pinctrl driver\n");

	if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
		if (value > 6)
			return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
		writel(value, sfp->padctl + IO_PADSHARE_SEL);
	}

	value = readl(sfp->padctl + IO_PADSHARE_SEL);
	switch (value) {
	case 0:
		sfp->gpios.pin_base = PAD_INVALID_GPIO;
		goto out_pinctrl_enable;
	case 1:
		sfp->gpios.pin_base = PAD_GPIO(0);
		break;
	case 2:
		sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
		break;
	case 3:
		sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
		break;
	case 4: case 5: case 6:
		sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
		break;
	default:
		return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
	}

	sfp->gc.label = dev_name(dev);
	sfp->gc.owner = THIS_MODULE;
	sfp->gc.request = starfive_gpio_request;
	sfp->gc.free = starfive_gpio_free;
	sfp->gc.get_direction = starfive_gpio_get_direction;
	sfp->gc.direction_input = starfive_gpio_direction_input;
	sfp->gc.direction_output = starfive_gpio_direction_output;
	sfp->gc.get = starfive_gpio_get;
	sfp->gc.set = starfive_gpio_set;
	sfp->gc.set_config = starfive_gpio_set_config;
	sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
	sfp->gc.base = -1;
	sfp->gc.ngpio = NR_GPIOS;

	starfive_irq_chip.parent_device = dev;
	starfive_irq_chip.name = sfp->gc.label;

	sfp->gc.irq.chip = &starfive_irq_chip;
	sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
	sfp->gc.irq.num_parents = 1;
	sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
					   sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
	if (!sfp->gc.irq.parents)
		return -ENOMEM;
	sfp->gc.irq.default_type = IRQ_TYPE_NONE;
	sfp->gc.irq.handler = handle_bad_irq;
	sfp->gc.irq.init_hw = starfive_gpio_init_hw;

	ret = platform_get_irq(pdev, 0);
	if (ret < 0)
		return ret;
	sfp->gc.irq.parents[0] = ret;

	ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
	if (ret)
		return dev_err_probe(dev, ret, "could not register gpiochip\n");

out_pinctrl_enable:
	return pinctrl_enable(sfp->pctl);
}