in ptp_idt82p33.c [705:745]
static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns)
{
struct idt82p33_channel *channel =
container_of(ptp, struct idt82p33_channel, caps);
struct idt82p33 *idt82p33 = channel->idt82p33;
s64 offset_regval, offset_fs;
u8 val[4] = {0};
int err;
offset_fs = (s64)(-offset_ns) * 1000000;
if (offset_fs > WRITE_PHASE_OFFSET_LIMIT)
offset_fs = WRITE_PHASE_OFFSET_LIMIT;
else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT)
offset_fs = -WRITE_PHASE_OFFSET_LIMIT;
/* Convert from phaseoffset_fs to register value */
offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL);
val[0] = offset_regval & 0xFF;
val[1] = (offset_regval >> 8) & 0xFF;
val[2] = (offset_regval >> 16) & 0xFF;
val[3] = (offset_regval >> 24) & 0x1F;
val[3] |= PH_OFFSET_EN;
mutex_lock(&idt82p33->reg_lock);
err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH);
if (err) {
dev_err(&idt82p33->client->dev,
"Failed in %s with err %d!\n", __func__, err);
goto out;
}
err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val,
sizeof(val));
out:
mutex_unlock(&idt82p33->reg_lock);
return err;
}