in ptp_idt82p33.c [832:862]
static int idt82p33_channel_init(struct idt82p33_channel *channel, int index)
{
switch (index) {
case 0:
channel->dpll_tod_cnfg = DPLL1_TOD_CNFG;
channel->dpll_tod_trigger = DPLL1_TOD_TRIGGER;
channel->dpll_tod_sts = DPLL1_TOD_STS;
channel->dpll_mode_cnfg = DPLL1_OPERATING_MODE_CNFG;
channel->dpll_freq_cnfg = DPLL1_HOLDOVER_FREQ_CNFG;
channel->dpll_phase_cnfg = DPLL1_PHASE_OFFSET_CNFG;
channel->dpll_sync_cnfg = DPLL1_SYNC_EDGE_CNFG;
channel->dpll_input_mode_cnfg = DPLL1_INPUT_MODE_CNFG;
break;
case 1:
channel->dpll_tod_cnfg = DPLL2_TOD_CNFG;
channel->dpll_tod_trigger = DPLL2_TOD_TRIGGER;
channel->dpll_tod_sts = DPLL2_TOD_STS;
channel->dpll_mode_cnfg = DPLL2_OPERATING_MODE_CNFG;
channel->dpll_freq_cnfg = DPLL2_HOLDOVER_FREQ_CNFG;
channel->dpll_phase_cnfg = DPLL2_PHASE_OFFSET_CNFG;
channel->dpll_sync_cnfg = DPLL2_SYNC_EDGE_CNFG;
channel->dpll_input_mode_cnfg = DPLL2_INPUT_MODE_CNFG;
break;
default:
return -EINVAL;
}
channel->current_freq_ppb = 0;
return 0;
}