static int mtk_spmi_probe()

in spmi-mtk-pmif.c [433:504]


static int mtk_spmi_probe(struct platform_device *pdev)
{
	struct pmif *arb;
	struct spmi_controller *ctrl;
	int err, i;
	u32 chan_offset;

	ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*arb));
	if (!ctrl)
		return -ENOMEM;

	arb = spmi_controller_get_drvdata(ctrl);
	arb->data = device_get_match_data(&pdev->dev);
	if (!arb->data) {
		err = -EINVAL;
		dev_err(&pdev->dev, "Cannot get drv_data\n");
		goto err_put_ctrl;
	}

	arb->base = devm_platform_ioremap_resource_byname(pdev, "pmif");
	if (IS_ERR(arb->base)) {
		err = PTR_ERR(arb->base);
		goto err_put_ctrl;
	}

	arb->spmimst_base = devm_platform_ioremap_resource_byname(pdev, "spmimst");
	if (IS_ERR(arb->spmimst_base)) {
		err = PTR_ERR(arb->spmimst_base);
		goto err_put_ctrl;
	}

	arb->nclks = ARRAY_SIZE(pmif_clock_names);
	for (i = 0; i < arb->nclks; i++)
		arb->clks[i].id = pmif_clock_names[i];

	err = devm_clk_bulk_get(&pdev->dev, arb->nclks, arb->clks);
	if (err) {
		dev_err(&pdev->dev, "Failed to get clocks: %d\n", err);
		goto err_put_ctrl;
	}

	err = clk_bulk_prepare_enable(arb->nclks, arb->clks);
	if (err) {
		dev_err(&pdev->dev, "Failed to enable clocks: %d\n", err);
		goto err_put_ctrl;
	}

	ctrl->cmd = pmif_arb_cmd;
	ctrl->read_cmd = pmif_spmi_read_cmd;
	ctrl->write_cmd = pmif_spmi_write_cmd;

	chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan;
	arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset;
	arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset;
	arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset;
	arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset;
	arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset;

	platform_set_drvdata(pdev, ctrl);

	err = spmi_controller_add(ctrl);
	if (err)
		goto err_domain_remove;

	return 0;

err_domain_remove:
	clk_bulk_disable_unprepare(arb->nclks, arb->clks);
err_put_ctrl:
	spmi_controller_put(ctrl);
	return err;
}