in pci.c [84:166]
int ssb_pci_xtal(struct ssb_bus *bus, u32 what, int turn_on)
{
int err;
u32 in, out, outenable;
u16 pci_status;
if (bus->bustype != SSB_BUSTYPE_PCI)
return 0;
err = pci_read_config_dword(bus->host_pci, SSB_GPIO_IN, &in);
if (err)
goto err_pci;
err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &out);
if (err)
goto err_pci;
err = pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, &outenable);
if (err)
goto err_pci;
outenable |= what;
if (turn_on) {
/* Avoid glitching the clock if GPRS is already using it.
* We can't actually read the state of the PLLPD so we infer it
* by the value of XTAL_PU which *is* readable via gpioin.
*/
if (!(in & SSB_GPIO_XTAL)) {
if (what & SSB_GPIO_XTAL) {
/* Turn the crystal on */
out |= SSB_GPIO_XTAL;
if (what & SSB_GPIO_PLL)
out |= SSB_GPIO_PLL;
err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
if (err)
goto err_pci;
err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE,
outenable);
if (err)
goto err_pci;
msleep(1);
}
if (what & SSB_GPIO_PLL) {
/* Turn the PLL on */
out &= ~SSB_GPIO_PLL;
err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
if (err)
goto err_pci;
msleep(5);
}
}
err = pci_read_config_word(bus->host_pci, PCI_STATUS, &pci_status);
if (err)
goto err_pci;
pci_status &= ~PCI_STATUS_SIG_TARGET_ABORT;
err = pci_write_config_word(bus->host_pci, PCI_STATUS, pci_status);
if (err)
goto err_pci;
} else {
if (what & SSB_GPIO_XTAL) {
/* Turn the crystal off */
out &= ~SSB_GPIO_XTAL;
}
if (what & SSB_GPIO_PLL) {
/* Turn the PLL off */
out |= SSB_GPIO_PLL;
}
err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT, out);
if (err)
goto err_pci;
err = pci_write_config_dword(bus->host_pci, SSB_GPIO_OUT_ENABLE, outenable);
if (err)
goto err_pci;
}
out:
return err;
err_pci:
pr_err("Error: ssb_pci_xtal() could not access PCI config space!\n");
err = -EBUSY;
goto out;
}