static int brcmuart_probe()

in serial/8250/8250_bcm7271.c [934:1123]


static int brcmuart_probe(struct platform_device *pdev)
{
	struct resource *regs;
	struct device_node *np = pdev->dev.of_node;
	const struct of_device_id *of_id = NULL;
	struct uart_8250_port *new_port;
	struct device *dev = &pdev->dev;
	struct brcmuart_priv *priv;
	struct clk *baud_mux_clk;
	struct uart_8250_port up;
	int irq;
	void __iomem *membase = NULL;
	resource_size_t mapbase = 0;
	u32 clk_rate = 0;
	int ret;
	int x;
	int dma_irq;
	static const char * const reg_names[REGS_MAX] = {
		"uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb"
	};

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;
	priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv),
			GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	of_id = of_match_node(brcmuart_dt_ids, np);
	if (!of_id || !of_id->data)
		priv->rate_table = brcmstb_rate_table;
	else
		priv->rate_table = of_id->data;

	for (x = 0; x < REGS_MAX; x++) {
		regs = platform_get_resource_byname(pdev, IORESOURCE_MEM,
						reg_names[x]);
		if (!regs)
			break;
		priv->regs[x] =	devm_ioremap(dev, regs->start,
					     resource_size(regs));
		if (!priv->regs[x])
			return -ENOMEM;
		if (x == REGS_8250) {
			mapbase = regs->start;
			membase = priv->regs[x];
		}
	}

	/* We should have just the uart base registers or all the registers */
	if (x != 1 && x != REGS_MAX) {
		dev_warn(dev, "%s registers not specified\n", reg_names[x]);
		return -EINVAL;
	}

	/* if the DMA registers were specified, try to enable DMA */
	if (x > REGS_DMA_RX) {
		if (brcmuart_arbitration(priv, 1) == 0) {
			u32 txrev = 0;
			u32 rxrev = 0;

			txrev = udma_readl(priv, REGS_DMA_RX, UDMA_RX_REVISION);
			rxrev = udma_readl(priv, REGS_DMA_TX, UDMA_TX_REVISION);
			if ((txrev >= UDMA_TX_REVISION_REQUIRED) &&
				(rxrev >= UDMA_RX_REVISION_REQUIRED)) {

				/* Enable the use of the DMA hardware */
				priv->dma_enabled = true;
			} else {
				brcmuart_arbitration(priv, 0);
				dev_err(dev,
					"Unsupported DMA Hardware Revision\n");
			}
		} else {
			dev_err(dev,
				"Timeout arbitrating for UART DMA hardware\n");
		}
	}

	of_property_read_u32(np, "clock-frequency", &clk_rate);

	/* See if a Baud clock has been specified */
	baud_mux_clk = of_clk_get_by_name(np, "sw_baud");
	if (IS_ERR(baud_mux_clk)) {
		if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER)
			return -EPROBE_DEFER;
		dev_dbg(dev, "BAUD MUX clock not specified\n");
	} else {
		dev_dbg(dev, "BAUD MUX clock found\n");
		ret = clk_prepare_enable(baud_mux_clk);
		if (ret)
			return ret;
		priv->baud_mux_clk = baud_mux_clk;
		init_real_clk_rates(dev, priv);
		clk_rate = priv->default_mux_rate;
	}

	if (clk_rate == 0) {
		dev_err(dev, "clock-frequency or clk not defined\n");
		return -EINVAL;
	}

	dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not ");

	memset(&up, 0, sizeof(up));
	up.port.type = PORT_16550A;
	up.port.uartclk = clk_rate;
	up.port.dev = dev;
	up.port.mapbase = mapbase;
	up.port.membase = membase;
	up.port.irq = irq;
	up.port.handle_irq = brcmuart_handle_irq;
	up.port.regshift = 2;
	up.port.iotype = of_device_is_big_endian(np) ?
		UPIO_MEM32BE : UPIO_MEM32;
	up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF
		| UPF_FIXED_PORT | UPF_FIXED_TYPE;
	up.port.dev = dev;
	up.port.private_data = priv;
	up.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
	up.port.fifosize = 32;

	/* Check for a fixed line number */
	ret = of_alias_get_id(np, "serial");
	if (ret >= 0)
		up.port.line = ret;

	/* setup HR timer */
	hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
	priv->hrt.function = brcmuart_hrtimer_func;

	up.port.shutdown = brcmuart_shutdown;
	up.port.startup = brcmuart_startup;
	up.port.throttle = brcmuart_throttle;
	up.port.unthrottle = brcmuart_unthrottle;
	up.port.set_termios = brcmstb_set_termios;

	if (priv->dma_enabled) {
		priv->rx_size = RX_BUF_SIZE * RX_BUFS_COUNT;
		priv->rx_bufs = dma_alloc_coherent(dev,
						   priv->rx_size,
						   &priv->rx_addr, GFP_KERNEL);
		if (!priv->rx_bufs) {
			ret = -ENOMEM;
			goto err;
		}
		priv->tx_size = UART_XMIT_SIZE;
		priv->tx_buf = dma_alloc_coherent(dev,
						  priv->tx_size,
						  &priv->tx_addr, GFP_KERNEL);
		if (!priv->tx_buf) {
			ret = -ENOMEM;
			goto err;
		}
	}

	ret = serial8250_register_8250_port(&up);
	if (ret < 0) {
		dev_err(dev, "unable to register 8250 port\n");
		goto err;
	}
	priv->line = ret;
	new_port = serial8250_get_port(ret);
	priv->up = &new_port->port;
	if (priv->dma_enabled) {
		dma_irq = platform_get_irq_byname(pdev,  "dma");
		if (dma_irq < 0) {
			ret = dma_irq;
			dev_err(dev, "no IRQ resource info\n");
			goto err1;
		}
		ret = devm_request_irq(dev, dma_irq, brcmuart_isr,
				IRQF_SHARED, "uart DMA irq", &new_port->port);
		if (ret) {
			dev_err(dev, "unable to register IRQ handler\n");
			goto err1;
		}
	}
	platform_set_drvdata(pdev, priv);
	brcmuart_init_debugfs(priv, dev_name(&pdev->dev));
	return 0;

err1:
	serial8250_unregister_port(priv->line);
err:
	brcmuart_free_bufs(dev, priv);
	brcmuart_arbitration(priv, 0);
	return ret;
}