in platform/reset/vfio_platform_amdxgbe.c [48:110]
static int vfio_platform_amdxgbe_reset(struct vfio_platform_device *vdev)
{
struct vfio_platform_region *xgmac_regs = &vdev->regions[0];
struct vfio_platform_region *xpcs_regs = &vdev->regions[1];
u32 dma_mr_value, pcs_value, value;
unsigned int count;
if (!xgmac_regs->ioaddr) {
xgmac_regs->ioaddr =
ioremap(xgmac_regs->addr, xgmac_regs->size);
if (!xgmac_regs->ioaddr)
return -ENOMEM;
}
if (!xpcs_regs->ioaddr) {
xpcs_regs->ioaddr =
ioremap(xpcs_regs->addr, xpcs_regs->size);
if (!xpcs_regs->ioaddr)
return -ENOMEM;
}
/* reset the PHY through MDIO*/
pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1);
pcs_value |= MDIO_CTRL1_RESET;
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_PCS, MDIO_CTRL1, pcs_value);
count = 50;
do {
msleep(20);
pcs_value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_PCS,
MDIO_CTRL1);
} while ((pcs_value & MDIO_CTRL1_RESET) && --count);
if (pcs_value & MDIO_CTRL1_RESET)
dev_warn(vdev->device, "%s: XGBE PHY reset timeout\n",
__func__);
/* disable auto-negotiation */
value = xmdio_read(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1);
value &= ~MDIO_AN_CTRL1_ENABLE;
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_CTRL1, value);
/* disable AN IRQ */
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
/* clear AN IRQ */
xmdio_write(xpcs_regs->ioaddr, MDIO_MMD_AN, MDIO_AN_INT, 0);
/* MAC software reset */
dma_mr_value = ioread32(xgmac_regs->ioaddr + DMA_MR);
dma_mr_value |= 0x1;
iowrite32(dma_mr_value, xgmac_regs->ioaddr + DMA_MR);
usleep_range(10, 15);
count = 2000;
while (--count && (ioread32(xgmac_regs->ioaddr + DMA_MR) & 1))
usleep_range(500, 600);
if (!count)
dev_warn(vdev->device, "%s: MAC SW reset failed\n", __func__);
return 0;
}