in bridges/vme_tsi148.c [1516:1613]
static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
u32 aspace, u32 cycle, u32 dwidth)
{
u32 val;
val = be32_to_cpu(*attr);
/* Setup 2eSST speeds */
switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
case VME_2eSST160:
val |= TSI148_LCSR_DDAT_2eSSTM_160;
break;
case VME_2eSST267:
val |= TSI148_LCSR_DDAT_2eSSTM_267;
break;
case VME_2eSST320:
val |= TSI148_LCSR_DDAT_2eSSTM_320;
break;
}
/* Setup cycle types */
if (cycle & VME_SCT)
val |= TSI148_LCSR_DDAT_TM_SCT;
if (cycle & VME_BLT)
val |= TSI148_LCSR_DDAT_TM_BLT;
if (cycle & VME_MBLT)
val |= TSI148_LCSR_DDAT_TM_MBLT;
if (cycle & VME_2eVME)
val |= TSI148_LCSR_DDAT_TM_2eVME;
if (cycle & VME_2eSST)
val |= TSI148_LCSR_DDAT_TM_2eSST;
if (cycle & VME_2eSSTB) {
dev_err(dev, "Currently not setting Broadcast Select "
"Registers\n");
val |= TSI148_LCSR_DDAT_TM_2eSSTB;
}
/* Setup data width */
switch (dwidth) {
case VME_D16:
val |= TSI148_LCSR_DDAT_DBW_16;
break;
case VME_D32:
val |= TSI148_LCSR_DDAT_DBW_32;
break;
default:
dev_err(dev, "Invalid data width\n");
return -EINVAL;
}
/* Setup address space */
switch (aspace) {
case VME_A16:
val |= TSI148_LCSR_DDAT_AMODE_A16;
break;
case VME_A24:
val |= TSI148_LCSR_DDAT_AMODE_A24;
break;
case VME_A32:
val |= TSI148_LCSR_DDAT_AMODE_A32;
break;
case VME_A64:
val |= TSI148_LCSR_DDAT_AMODE_A64;
break;
case VME_CRCSR:
val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
break;
case VME_USER1:
val |= TSI148_LCSR_DDAT_AMODE_USER1;
break;
case VME_USER2:
val |= TSI148_LCSR_DDAT_AMODE_USER2;
break;
case VME_USER3:
val |= TSI148_LCSR_DDAT_AMODE_USER3;
break;
case VME_USER4:
val |= TSI148_LCSR_DDAT_AMODE_USER4;
break;
default:
dev_err(dev, "Invalid address space\n");
return -EINVAL;
}
if (cycle & VME_SUPER)
val |= TSI148_LCSR_DDAT_SUP;
if (cycle & VME_PROG)
val |= TSI148_LCSR_DDAT_PGM;
*attr = cpu_to_be32(val);
return 0;
}