devicetree/bindings/media/i2c/tda1997x.txt [58:117]:
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   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
		 * and Y[11:4] across 16bits in the same pixclk cycle.
		 */
		nxp,vidout-portcfg =
			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
			/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
			/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;

		port {
			tda1997x_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <16>;
				hsync-active = <1>;
				vsync-active = <1>;
				data-active = <1>;
			};
		};
	};
 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
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devicetree/bindings/media/i2c/tda1997x.txt [100:159]:
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   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
		 * and Y[11:4] across 16bits in the same pixclk cycle.
		 */
		nxp,vidout-portcfg =
			/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
			/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
			/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
			/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;

		port {
			tda1997x_to_ipu1_csi0_mux: endpoint {
				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
				bus-width = <16>;
				hsync-active = <1>;
				vsync-active = <1>;
				data-active = <1>;
			};
		};
	};
 - VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
   16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
	hdmi-receiver@48 {
		compatible = "nxp,tda19971";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_tda1997x>;
		reg = <0x48>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
		DOVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_1p8v>;
		DVDD-supply = <&reg_1p8v>;
		/* audio */
		#sound-dai-cells = <0>;
		nxp,audout-format = "i2s";
		nxp,audout-layout = <0>;
		nxp,audout-width = <16>;
		nxp,audout-mclk-fs = <128>;
		/*
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