in llvm/lib/Target/Mips/MipsSEISelLowering.cpp [1540:2291]
SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue();
switch (Intrinsic) {
default:
return SDValue();
case Intrinsic::mips_shilo:
return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
case Intrinsic::mips_dpau_h_qbl:
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
case Intrinsic::mips_dpau_h_qbr:
return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
case Intrinsic::mips_dpsu_h_qbl:
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
case Intrinsic::mips_dpsu_h_qbr:
return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
case Intrinsic::mips_dpa_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
case Intrinsic::mips_dps_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
case Intrinsic::mips_dpax_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
case Intrinsic::mips_dpsx_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
case Intrinsic::mips_mulsa_w_ph:
return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
case Intrinsic::mips_mult:
return lowerDSPIntr(Op, DAG, MipsISD::Mult);
case Intrinsic::mips_multu:
return lowerDSPIntr(Op, DAG, MipsISD::Multu);
case Intrinsic::mips_madd:
return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
case Intrinsic::mips_maddu:
return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
case Intrinsic::mips_msub:
return lowerDSPIntr(Op, DAG, MipsISD::MSub);
case Intrinsic::mips_msubu:
return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
case Intrinsic::mips_addv_b:
case Intrinsic::mips_addv_h:
case Intrinsic::mips_addv_w:
case Intrinsic::mips_addv_d:
return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_addvi_b:
case Intrinsic::mips_addvi_h:
case Intrinsic::mips_addvi_w:
case Intrinsic::mips_addvi_d:
return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_and_v:
return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_andi_b:
return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_bclr_b:
case Intrinsic::mips_bclr_h:
case Intrinsic::mips_bclr_w:
case Intrinsic::mips_bclr_d:
return lowerMSABitClear(Op, DAG);
case Intrinsic::mips_bclri_b:
case Intrinsic::mips_bclri_h:
case Intrinsic::mips_bclri_w:
case Intrinsic::mips_bclri_d:
return lowerMSABitClearImm(Op, DAG);
case Intrinsic::mips_binsli_b:
case Intrinsic::mips_binsli_h:
case Intrinsic::mips_binsli_w:
case Intrinsic::mips_binsli_d: {
// binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
EVT VecTy = Op->getValueType(0);
EVT EltTy = VecTy.getVectorElementType();
if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
report_fatal_error("Immediate out of range");
APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3) + 1);
return DAG.getNode(ISD::VSELECT, DL, VecTy,
DAG.getConstant(Mask, DL, VecTy, true),
Op->getOperand(2), Op->getOperand(1));
}
case Intrinsic::mips_binsri_b:
case Intrinsic::mips_binsri_h:
case Intrinsic::mips_binsri_w:
case Intrinsic::mips_binsri_d: {
// binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
EVT VecTy = Op->getValueType(0);
EVT EltTy = VecTy.getVectorElementType();
if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits())
report_fatal_error("Immediate out of range");
APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
Op->getConstantOperandVal(3) + 1);
return DAG.getNode(ISD::VSELECT, DL, VecTy,
DAG.getConstant(Mask, DL, VecTy, true),
Op->getOperand(2), Op->getOperand(1));
}
case Intrinsic::mips_bmnz_v:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
Op->getOperand(2), Op->getOperand(1));
case Intrinsic::mips_bmnzi_b:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
Op->getOperand(1));
case Intrinsic::mips_bmz_v:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_bmzi_b:
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_bneg_b:
case Intrinsic::mips_bneg_h:
case Intrinsic::mips_bneg_w:
case Intrinsic::mips_bneg_d: {
EVT VecTy = Op->getValueType(0);
SDValue One = DAG.getConstant(1, DL, VecTy);
return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
truncateVecElts(Op, DAG)));
}
case Intrinsic::mips_bnegi_b:
case Intrinsic::mips_bnegi_h:
case Intrinsic::mips_bnegi_w:
case Intrinsic::mips_bnegi_d:
return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
!Subtarget.isLittle());
case Intrinsic::mips_bnz_b:
case Intrinsic::mips_bnz_h:
case Intrinsic::mips_bnz_w:
case Intrinsic::mips_bnz_d:
return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_bnz_v:
return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_bsel_v:
// bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(3),
Op->getOperand(2));
case Intrinsic::mips_bseli_b:
// bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
Op->getOperand(2));
case Intrinsic::mips_bset_b:
case Intrinsic::mips_bset_h:
case Intrinsic::mips_bset_w:
case Intrinsic::mips_bset_d: {
EVT VecTy = Op->getValueType(0);
SDValue One = DAG.getConstant(1, DL, VecTy);
return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, DL, VecTy, One,
truncateVecElts(Op, DAG)));
}
case Intrinsic::mips_bseti_b:
case Intrinsic::mips_bseti_h:
case Intrinsic::mips_bseti_w:
case Intrinsic::mips_bseti_d:
return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
!Subtarget.isLittle());
case Intrinsic::mips_bz_b:
case Intrinsic::mips_bz_h:
case Intrinsic::mips_bz_w:
case Intrinsic::mips_bz_d:
return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_bz_v:
return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_ceq_b:
case Intrinsic::mips_ceq_h:
case Intrinsic::mips_ceq_w:
case Intrinsic::mips_ceq_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETEQ);
case Intrinsic::mips_ceqi_b:
case Intrinsic::mips_ceqi_h:
case Intrinsic::mips_ceqi_w:
case Intrinsic::mips_ceqi_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ);
case Intrinsic::mips_cle_s_b:
case Intrinsic::mips_cle_s_h:
case Intrinsic::mips_cle_s_w:
case Intrinsic::mips_cle_s_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETLE);
case Intrinsic::mips_clei_s_b:
case Intrinsic::mips_clei_s_h:
case Intrinsic::mips_clei_s_w:
case Intrinsic::mips_clei_s_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE);
case Intrinsic::mips_cle_u_b:
case Intrinsic::mips_cle_u_h:
case Intrinsic::mips_cle_u_w:
case Intrinsic::mips_cle_u_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETULE);
case Intrinsic::mips_clei_u_b:
case Intrinsic::mips_clei_u_h:
case Intrinsic::mips_clei_u_w:
case Intrinsic::mips_clei_u_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
case Intrinsic::mips_clt_s_b:
case Intrinsic::mips_clt_s_h:
case Intrinsic::mips_clt_s_w:
case Intrinsic::mips_clt_s_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETLT);
case Intrinsic::mips_clti_s_b:
case Intrinsic::mips_clti_s_h:
case Intrinsic::mips_clti_s_w:
case Intrinsic::mips_clti_s_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT);
case Intrinsic::mips_clt_u_b:
case Intrinsic::mips_clt_u_h:
case Intrinsic::mips_clt_u_w:
case Intrinsic::mips_clt_u_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETULT);
case Intrinsic::mips_clti_u_b:
case Intrinsic::mips_clti_u_h:
case Intrinsic::mips_clti_u_w:
case Intrinsic::mips_clti_u_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
case Intrinsic::mips_copy_s_b:
case Intrinsic::mips_copy_s_h:
case Intrinsic::mips_copy_s_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
case Intrinsic::mips_copy_s_d:
if (Subtarget.hasMips64())
// Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
else {
// Lower into the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
}
case Intrinsic::mips_copy_u_b:
case Intrinsic::mips_copy_u_h:
case Intrinsic::mips_copy_u_w:
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
case Intrinsic::mips_copy_u_d:
if (Subtarget.hasMips64())
// Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
else {
// Lower into the generic EXTRACT_VECTOR_ELT node and let the type
// legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
// Note: When i64 is illegal, this results in copy_s.w instructions
// instead of copy_u.w instructions. This makes no difference to the
// behaviour since i64 is only illegal when the register file is 32-bit.
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
}
case Intrinsic::mips_div_s_b:
case Intrinsic::mips_div_s_h:
case Intrinsic::mips_div_s_w:
case Intrinsic::mips_div_s_d:
return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_div_u_b:
case Intrinsic::mips_div_u_h:
case Intrinsic::mips_div_u_w:
case Intrinsic::mips_div_u_d:
return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_fadd_w:
case Intrinsic::mips_fadd_d:
// TODO: If intrinsics have fast-math-flags, propagate them.
return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
// Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
case Intrinsic::mips_fceq_w:
case Intrinsic::mips_fceq_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETOEQ);
case Intrinsic::mips_fcle_w:
case Intrinsic::mips_fcle_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETOLE);
case Intrinsic::mips_fclt_w:
case Intrinsic::mips_fclt_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETOLT);
case Intrinsic::mips_fcne_w:
case Intrinsic::mips_fcne_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETONE);
case Intrinsic::mips_fcor_w:
case Intrinsic::mips_fcor_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETO);
case Intrinsic::mips_fcueq_w:
case Intrinsic::mips_fcueq_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETUEQ);
case Intrinsic::mips_fcule_w:
case Intrinsic::mips_fcule_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETULE);
case Intrinsic::mips_fcult_w:
case Intrinsic::mips_fcult_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETULT);
case Intrinsic::mips_fcun_w:
case Intrinsic::mips_fcun_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETUO);
case Intrinsic::mips_fcune_w:
case Intrinsic::mips_fcune_d:
return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2), ISD::SETUNE);
case Intrinsic::mips_fdiv_w:
case Intrinsic::mips_fdiv_d:
// TODO: If intrinsics have fast-math-flags, propagate them.
return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_ffint_u_w:
case Intrinsic::mips_ffint_u_d:
return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_ffint_s_w:
case Intrinsic::mips_ffint_s_d:
return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_fill_b:
case Intrinsic::mips_fill_h:
case Intrinsic::mips_fill_w:
case Intrinsic::mips_fill_d: {
EVT ResTy = Op->getValueType(0);
SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
Op->getOperand(1));
// If ResTy is v2i64 then the type legalizer will break this node down into
// an equivalent v4i32.
return DAG.getBuildVector(ResTy, DL, Ops);
}
case Intrinsic::mips_fexp2_w:
case Intrinsic::mips_fexp2_d: {
// TODO: If intrinsics have fast-math-flags, propagate them.
EVT ResTy = Op->getValueType(0);
return DAG.getNode(
ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
}
case Intrinsic::mips_flog2_w:
case Intrinsic::mips_flog2_d:
return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
case Intrinsic::mips_fmadd_w:
case Intrinsic::mips_fmadd_d:
return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
case Intrinsic::mips_fmul_w:
case Intrinsic::mips_fmul_d:
// TODO: If intrinsics have fast-math-flags, propagate them.
return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_fmsub_w:
case Intrinsic::mips_fmsub_d: {
// TODO: If intrinsics have fast-math-flags, propagate them.
return DAG.getNode(MipsISD::FMS, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
}
case Intrinsic::mips_frint_w:
case Intrinsic::mips_frint_d:
return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
case Intrinsic::mips_fsqrt_w:
case Intrinsic::mips_fsqrt_d:
return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
case Intrinsic::mips_fsub_w:
case Intrinsic::mips_fsub_d:
// TODO: If intrinsics have fast-math-flags, propagate them.
return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_ftrunc_u_w:
case Intrinsic::mips_ftrunc_u_d:
return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_ftrunc_s_w:
case Intrinsic::mips_ftrunc_s_d:
return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
Op->getOperand(1));
case Intrinsic::mips_ilvev_b:
case Intrinsic::mips_ilvev_h:
case Intrinsic::mips_ilvev_w:
case Intrinsic::mips_ilvev_d:
return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_ilvl_b:
case Intrinsic::mips_ilvl_h:
case Intrinsic::mips_ilvl_w:
case Intrinsic::mips_ilvl_d:
return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_ilvod_b:
case Intrinsic::mips_ilvod_h:
case Intrinsic::mips_ilvod_w:
case Intrinsic::mips_ilvod_d:
return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_ilvr_b:
case Intrinsic::mips_ilvr_h:
case Intrinsic::mips_ilvr_w:
case Intrinsic::mips_ilvr_d:
return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_insert_b:
case Intrinsic::mips_insert_h:
case Intrinsic::mips_insert_w:
case Intrinsic::mips_insert_d:
return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
case Intrinsic::mips_insve_b:
case Intrinsic::mips_insve_h:
case Intrinsic::mips_insve_w:
case Intrinsic::mips_insve_d: {
// Report an error for out of range values.
int64_t Max;
switch (Intrinsic) {
case Intrinsic::mips_insve_b: Max = 15; break;
case Intrinsic::mips_insve_h: Max = 7; break;
case Intrinsic::mips_insve_w: Max = 3; break;
case Intrinsic::mips_insve_d: Max = 1; break;
default: llvm_unreachable("Unmatched intrinsic");
}
int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
if (Value < 0 || Value > Max)
report_fatal_error("Immediate out of range");
return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
DAG.getConstant(0, DL, MVT::i32));
}
case Intrinsic::mips_ldi_b:
case Intrinsic::mips_ldi_h:
case Intrinsic::mips_ldi_w:
case Intrinsic::mips_ldi_d:
return lowerMSASplatImm(Op, 1, DAG, true);
case Intrinsic::mips_lsa:
case Intrinsic::mips_dlsa: {
EVT ResTy = Op->getValueType(0);
return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
Op->getOperand(2), Op->getOperand(3)));
}
case Intrinsic::mips_maddv_b:
case Intrinsic::mips_maddv_h:
case Intrinsic::mips_maddv_w:
case Intrinsic::mips_maddv_d: {
EVT ResTy = Op->getValueType(0);
return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
Op->getOperand(2), Op->getOperand(3)));
}
case Intrinsic::mips_max_s_b:
case Intrinsic::mips_max_s_h:
case Intrinsic::mips_max_s_w:
case Intrinsic::mips_max_s_d:
return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_max_u_b:
case Intrinsic::mips_max_u_h:
case Intrinsic::mips_max_u_w:
case Intrinsic::mips_max_u_d:
return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_maxi_s_b:
case Intrinsic::mips_maxi_s_h:
case Intrinsic::mips_maxi_s_w:
case Intrinsic::mips_maxi_s_d:
return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
case Intrinsic::mips_maxi_u_b:
case Intrinsic::mips_maxi_u_h:
case Intrinsic::mips_maxi_u_w:
case Intrinsic::mips_maxi_u_d:
return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_min_s_b:
case Intrinsic::mips_min_s_h:
case Intrinsic::mips_min_s_w:
case Intrinsic::mips_min_s_d:
return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_min_u_b:
case Intrinsic::mips_min_u_h:
case Intrinsic::mips_min_u_w:
case Intrinsic::mips_min_u_d:
return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_mini_s_b:
case Intrinsic::mips_mini_s_h:
case Intrinsic::mips_mini_s_w:
case Intrinsic::mips_mini_s_d:
return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true));
case Intrinsic::mips_mini_u_b:
case Intrinsic::mips_mini_u_h:
case Intrinsic::mips_mini_u_w:
case Intrinsic::mips_mini_u_d:
return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_mod_s_b:
case Intrinsic::mips_mod_s_h:
case Intrinsic::mips_mod_s_w:
case Intrinsic::mips_mod_s_d:
return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_mod_u_b:
case Intrinsic::mips_mod_u_h:
case Intrinsic::mips_mod_u_w:
case Intrinsic::mips_mod_u_d:
return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_mulv_b:
case Intrinsic::mips_mulv_h:
case Intrinsic::mips_mulv_w:
case Intrinsic::mips_mulv_d:
return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_msubv_b:
case Intrinsic::mips_msubv_h:
case Intrinsic::mips_msubv_w:
case Intrinsic::mips_msubv_d: {
EVT ResTy = Op->getValueType(0);
return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
Op->getOperand(2), Op->getOperand(3)));
}
case Intrinsic::mips_nlzc_b:
case Intrinsic::mips_nlzc_h:
case Intrinsic::mips_nlzc_w:
case Intrinsic::mips_nlzc_d:
return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
case Intrinsic::mips_nor_v: {
SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
return DAG.getNOT(DL, Res, Res->getValueType(0));
}
case Intrinsic::mips_nori_b: {
SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
Op->getOperand(1),
lowerMSASplatImm(Op, 2, DAG));
return DAG.getNOT(DL, Res, Res->getValueType(0));
}
case Intrinsic::mips_or_v:
return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_ori_b:
return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_pckev_b:
case Intrinsic::mips_pckev_h:
case Intrinsic::mips_pckev_w:
case Intrinsic::mips_pckev_d:
return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_pckod_b:
case Intrinsic::mips_pckod_h:
case Intrinsic::mips_pckod_w:
case Intrinsic::mips_pckod_d:
return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2));
case Intrinsic::mips_pcnt_b:
case Intrinsic::mips_pcnt_h:
case Intrinsic::mips_pcnt_w:
case Intrinsic::mips_pcnt_d:
return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
case Intrinsic::mips_sat_s_b:
case Intrinsic::mips_sat_s_h:
case Intrinsic::mips_sat_s_w:
case Intrinsic::mips_sat_s_d:
case Intrinsic::mips_sat_u_b:
case Intrinsic::mips_sat_u_h:
case Intrinsic::mips_sat_u_w:
case Intrinsic::mips_sat_u_d: {
// Report an error for out of range values.
int64_t Max;
switch (Intrinsic) {
case Intrinsic::mips_sat_s_b:
case Intrinsic::mips_sat_u_b: Max = 7; break;
case Intrinsic::mips_sat_s_h:
case Intrinsic::mips_sat_u_h: Max = 15; break;
case Intrinsic::mips_sat_s_w:
case Intrinsic::mips_sat_u_w: Max = 31; break;
case Intrinsic::mips_sat_s_d:
case Intrinsic::mips_sat_u_d: Max = 63; break;
default: llvm_unreachable("Unmatched intrinsic");
}
int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
if (Value < 0 || Value > Max)
report_fatal_error("Immediate out of range");
return SDValue();
}
case Intrinsic::mips_shf_b:
case Intrinsic::mips_shf_h:
case Intrinsic::mips_shf_w: {
int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
if (Value < 0 || Value > 255)
report_fatal_error("Immediate out of range");
return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
Op->getOperand(2), Op->getOperand(1));
}
case Intrinsic::mips_sldi_b:
case Intrinsic::mips_sldi_h:
case Intrinsic::mips_sldi_w:
case Intrinsic::mips_sldi_d: {
// Report an error for out of range values.
int64_t Max;
switch (Intrinsic) {
case Intrinsic::mips_sldi_b: Max = 15; break;
case Intrinsic::mips_sldi_h: Max = 7; break;
case Intrinsic::mips_sldi_w: Max = 3; break;
case Intrinsic::mips_sldi_d: Max = 1; break;
default: llvm_unreachable("Unmatched intrinsic");
}
int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue();
if (Value < 0 || Value > Max)
report_fatal_error("Immediate out of range");
return SDValue();
}
case Intrinsic::mips_sll_b:
case Intrinsic::mips_sll_h:
case Intrinsic::mips_sll_w:
case Intrinsic::mips_sll_d:
return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
truncateVecElts(Op, DAG));
case Intrinsic::mips_slli_b:
case Intrinsic::mips_slli_h:
case Intrinsic::mips_slli_w:
case Intrinsic::mips_slli_d:
return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_splat_b:
case Intrinsic::mips_splat_h:
case Intrinsic::mips_splat_w:
case Intrinsic::mips_splat_d:
// We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
// masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
// EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
// Instead we lower to MipsISD::VSHF and match from there.
return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
Op->getOperand(1));
case Intrinsic::mips_splati_b:
case Intrinsic::mips_splati_h:
case Intrinsic::mips_splati_w:
case Intrinsic::mips_splati_d:
return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
Op->getOperand(1));
case Intrinsic::mips_sra_b:
case Intrinsic::mips_sra_h:
case Intrinsic::mips_sra_w:
case Intrinsic::mips_sra_d:
return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
truncateVecElts(Op, DAG));
case Intrinsic::mips_srai_b:
case Intrinsic::mips_srai_h:
case Intrinsic::mips_srai_w:
case Intrinsic::mips_srai_d:
return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_srari_b:
case Intrinsic::mips_srari_h:
case Intrinsic::mips_srari_w:
case Intrinsic::mips_srari_d: {
// Report an error for out of range values.
int64_t Max;
switch (Intrinsic) {
case Intrinsic::mips_srari_b: Max = 7; break;
case Intrinsic::mips_srari_h: Max = 15; break;
case Intrinsic::mips_srari_w: Max = 31; break;
case Intrinsic::mips_srari_d: Max = 63; break;
default: llvm_unreachable("Unmatched intrinsic");
}
int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
if (Value < 0 || Value > Max)
report_fatal_error("Immediate out of range");
return SDValue();
}
case Intrinsic::mips_srl_b:
case Intrinsic::mips_srl_h:
case Intrinsic::mips_srl_w:
case Intrinsic::mips_srl_d:
return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
truncateVecElts(Op, DAG));
case Intrinsic::mips_srli_b:
case Intrinsic::mips_srli_h:
case Intrinsic::mips_srli_w:
case Intrinsic::mips_srli_d:
return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_srlri_b:
case Intrinsic::mips_srlri_h:
case Intrinsic::mips_srlri_w:
case Intrinsic::mips_srlri_d: {
// Report an error for out of range values.
int64_t Max;
switch (Intrinsic) {
case Intrinsic::mips_srlri_b: Max = 7; break;
case Intrinsic::mips_srlri_h: Max = 15; break;
case Intrinsic::mips_srlri_w: Max = 31; break;
case Intrinsic::mips_srlri_d: Max = 63; break;
default: llvm_unreachable("Unmatched intrinsic");
}
int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue();
if (Value < 0 || Value > Max)
report_fatal_error("Immediate out of range");
return SDValue();
}
case Intrinsic::mips_subv_b:
case Intrinsic::mips_subv_h:
case Intrinsic::mips_subv_w:
case Intrinsic::mips_subv_d:
return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_subvi_b:
case Intrinsic::mips_subvi_h:
case Intrinsic::mips_subvi_w:
case Intrinsic::mips_subvi_d:
return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::mips_vshf_b:
case Intrinsic::mips_vshf_h:
case Intrinsic::mips_vshf_w:
case Intrinsic::mips_vshf_d:
return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
case Intrinsic::mips_xor_v:
return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
Op->getOperand(2));
case Intrinsic::mips_xori_b:
return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
case Intrinsic::thread_pointer: {
EVT PtrVT = getPointerTy(DAG.getDataLayout());
return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
}
}
}