in llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp [237:657]
static Optional<LoadInfo> getLoadInfo(const MachineInstr &MI) {
int DestRegIdx;
int BaseRegIdx;
int OffsetIdx;
bool IsPrePost;
switch (MI.getOpcode()) {
default:
return None;
case AArch64::LD1i64:
case AArch64::LD2i64:
DestRegIdx = 0;
BaseRegIdx = 3;
OffsetIdx = -1;
IsPrePost = false;
break;
case AArch64::LD1i8:
case AArch64::LD1i16:
case AArch64::LD1i32:
case AArch64::LD2i8:
case AArch64::LD2i16:
case AArch64::LD2i32:
case AArch64::LD3i8:
case AArch64::LD3i16:
case AArch64::LD3i32:
case AArch64::LD3i64:
case AArch64::LD4i8:
case AArch64::LD4i16:
case AArch64::LD4i32:
case AArch64::LD4i64:
DestRegIdx = -1;
BaseRegIdx = 3;
OffsetIdx = -1;
IsPrePost = false;
break;
case AArch64::LD1Onev1d:
case AArch64::LD1Onev2s:
case AArch64::LD1Onev4h:
case AArch64::LD1Onev8b:
case AArch64::LD1Onev2d:
case AArch64::LD1Onev4s:
case AArch64::LD1Onev8h:
case AArch64::LD1Onev16b:
case AArch64::LD1Rv1d:
case AArch64::LD1Rv2s:
case AArch64::LD1Rv4h:
case AArch64::LD1Rv8b:
case AArch64::LD1Rv2d:
case AArch64::LD1Rv4s:
case AArch64::LD1Rv8h:
case AArch64::LD1Rv16b:
DestRegIdx = 0;
BaseRegIdx = 1;
OffsetIdx = -1;
IsPrePost = false;
break;
case AArch64::LD1Twov1d:
case AArch64::LD1Twov2s:
case AArch64::LD1Twov4h:
case AArch64::LD1Twov8b:
case AArch64::LD1Twov2d:
case AArch64::LD1Twov4s:
case AArch64::LD1Twov8h:
case AArch64::LD1Twov16b:
case AArch64::LD1Threev1d:
case AArch64::LD1Threev2s:
case AArch64::LD1Threev4h:
case AArch64::LD1Threev8b:
case AArch64::LD1Threev2d:
case AArch64::LD1Threev4s:
case AArch64::LD1Threev8h:
case AArch64::LD1Threev16b:
case AArch64::LD1Fourv1d:
case AArch64::LD1Fourv2s:
case AArch64::LD1Fourv4h:
case AArch64::LD1Fourv8b:
case AArch64::LD1Fourv2d:
case AArch64::LD1Fourv4s:
case AArch64::LD1Fourv8h:
case AArch64::LD1Fourv16b:
case AArch64::LD2Twov2s:
case AArch64::LD2Twov4s:
case AArch64::LD2Twov8b:
case AArch64::LD2Twov2d:
case AArch64::LD2Twov4h:
case AArch64::LD2Twov8h:
case AArch64::LD2Twov16b:
case AArch64::LD2Rv1d:
case AArch64::LD2Rv2s:
case AArch64::LD2Rv4s:
case AArch64::LD2Rv8b:
case AArch64::LD2Rv2d:
case AArch64::LD2Rv4h:
case AArch64::LD2Rv8h:
case AArch64::LD2Rv16b:
case AArch64::LD3Threev2s:
case AArch64::LD3Threev4h:
case AArch64::LD3Threev8b:
case AArch64::LD3Threev2d:
case AArch64::LD3Threev4s:
case AArch64::LD3Threev8h:
case AArch64::LD3Threev16b:
case AArch64::LD3Rv1d:
case AArch64::LD3Rv2s:
case AArch64::LD3Rv4h:
case AArch64::LD3Rv8b:
case AArch64::LD3Rv2d:
case AArch64::LD3Rv4s:
case AArch64::LD3Rv8h:
case AArch64::LD3Rv16b:
case AArch64::LD4Fourv2s:
case AArch64::LD4Fourv4h:
case AArch64::LD4Fourv8b:
case AArch64::LD4Fourv2d:
case AArch64::LD4Fourv4s:
case AArch64::LD4Fourv8h:
case AArch64::LD4Fourv16b:
case AArch64::LD4Rv1d:
case AArch64::LD4Rv2s:
case AArch64::LD4Rv4h:
case AArch64::LD4Rv8b:
case AArch64::LD4Rv2d:
case AArch64::LD4Rv4s:
case AArch64::LD4Rv8h:
case AArch64::LD4Rv16b:
DestRegIdx = -1;
BaseRegIdx = 1;
OffsetIdx = -1;
IsPrePost = false;
break;
case AArch64::LD1i64_POST:
case AArch64::LD2i64_POST:
DestRegIdx = 1;
BaseRegIdx = 4;
OffsetIdx = 5;
IsPrePost = true;
break;
case AArch64::LD1i8_POST:
case AArch64::LD1i16_POST:
case AArch64::LD1i32_POST:
case AArch64::LD2i8_POST:
case AArch64::LD2i16_POST:
case AArch64::LD2i32_POST:
case AArch64::LD3i8_POST:
case AArch64::LD3i16_POST:
case AArch64::LD3i32_POST:
case AArch64::LD3i64_POST:
case AArch64::LD4i8_POST:
case AArch64::LD4i16_POST:
case AArch64::LD4i32_POST:
case AArch64::LD4i64_POST:
DestRegIdx = -1;
BaseRegIdx = 4;
OffsetIdx = 5;
IsPrePost = true;
break;
case AArch64::LD1Onev1d_POST:
case AArch64::LD1Onev2s_POST:
case AArch64::LD1Onev4h_POST:
case AArch64::LD1Onev8b_POST:
case AArch64::LD1Onev2d_POST:
case AArch64::LD1Onev4s_POST:
case AArch64::LD1Onev8h_POST:
case AArch64::LD1Onev16b_POST:
case AArch64::LD1Rv1d_POST:
case AArch64::LD1Rv2s_POST:
case AArch64::LD1Rv4h_POST:
case AArch64::LD1Rv8b_POST:
case AArch64::LD1Rv2d_POST:
case AArch64::LD1Rv4s_POST:
case AArch64::LD1Rv8h_POST:
case AArch64::LD1Rv16b_POST:
DestRegIdx = 1;
BaseRegIdx = 2;
OffsetIdx = 3;
IsPrePost = true;
break;
case AArch64::LD1Twov1d_POST:
case AArch64::LD1Twov2s_POST:
case AArch64::LD1Twov4h_POST:
case AArch64::LD1Twov8b_POST:
case AArch64::LD1Twov2d_POST:
case AArch64::LD1Twov4s_POST:
case AArch64::LD1Twov8h_POST:
case AArch64::LD1Twov16b_POST:
case AArch64::LD1Threev1d_POST:
case AArch64::LD1Threev2s_POST:
case AArch64::LD1Threev4h_POST:
case AArch64::LD1Threev8b_POST:
case AArch64::LD1Threev2d_POST:
case AArch64::LD1Threev4s_POST:
case AArch64::LD1Threev8h_POST:
case AArch64::LD1Threev16b_POST:
case AArch64::LD1Fourv1d_POST:
case AArch64::LD1Fourv2s_POST:
case AArch64::LD1Fourv4h_POST:
case AArch64::LD1Fourv8b_POST:
case AArch64::LD1Fourv2d_POST:
case AArch64::LD1Fourv4s_POST:
case AArch64::LD1Fourv8h_POST:
case AArch64::LD1Fourv16b_POST:
case AArch64::LD2Twov2s_POST:
case AArch64::LD2Twov4s_POST:
case AArch64::LD2Twov8b_POST:
case AArch64::LD2Twov2d_POST:
case AArch64::LD2Twov4h_POST:
case AArch64::LD2Twov8h_POST:
case AArch64::LD2Twov16b_POST:
case AArch64::LD2Rv1d_POST:
case AArch64::LD2Rv2s_POST:
case AArch64::LD2Rv4s_POST:
case AArch64::LD2Rv8b_POST:
case AArch64::LD2Rv2d_POST:
case AArch64::LD2Rv4h_POST:
case AArch64::LD2Rv8h_POST:
case AArch64::LD2Rv16b_POST:
case AArch64::LD3Threev2s_POST:
case AArch64::LD3Threev4h_POST:
case AArch64::LD3Threev8b_POST:
case AArch64::LD3Threev2d_POST:
case AArch64::LD3Threev4s_POST:
case AArch64::LD3Threev8h_POST:
case AArch64::LD3Threev16b_POST:
case AArch64::LD3Rv1d_POST:
case AArch64::LD3Rv2s_POST:
case AArch64::LD3Rv4h_POST:
case AArch64::LD3Rv8b_POST:
case AArch64::LD3Rv2d_POST:
case AArch64::LD3Rv4s_POST:
case AArch64::LD3Rv8h_POST:
case AArch64::LD3Rv16b_POST:
case AArch64::LD4Fourv2s_POST:
case AArch64::LD4Fourv4h_POST:
case AArch64::LD4Fourv8b_POST:
case AArch64::LD4Fourv2d_POST:
case AArch64::LD4Fourv4s_POST:
case AArch64::LD4Fourv8h_POST:
case AArch64::LD4Fourv16b_POST:
case AArch64::LD4Rv1d_POST:
case AArch64::LD4Rv2s_POST:
case AArch64::LD4Rv4h_POST:
case AArch64::LD4Rv8b_POST:
case AArch64::LD4Rv2d_POST:
case AArch64::LD4Rv4s_POST:
case AArch64::LD4Rv8h_POST:
case AArch64::LD4Rv16b_POST:
DestRegIdx = -1;
BaseRegIdx = 2;
OffsetIdx = 3;
IsPrePost = true;
break;
case AArch64::LDRBBroW:
case AArch64::LDRBBroX:
case AArch64::LDRBBui:
case AArch64::LDRBroW:
case AArch64::LDRBroX:
case AArch64::LDRBui:
case AArch64::LDRDl:
case AArch64::LDRDroW:
case AArch64::LDRDroX:
case AArch64::LDRDui:
case AArch64::LDRHHroW:
case AArch64::LDRHHroX:
case AArch64::LDRHHui:
case AArch64::LDRHroW:
case AArch64::LDRHroX:
case AArch64::LDRHui:
case AArch64::LDRQl:
case AArch64::LDRQroW:
case AArch64::LDRQroX:
case AArch64::LDRQui:
case AArch64::LDRSBWroW:
case AArch64::LDRSBWroX:
case AArch64::LDRSBWui:
case AArch64::LDRSBXroW:
case AArch64::LDRSBXroX:
case AArch64::LDRSBXui:
case AArch64::LDRSHWroW:
case AArch64::LDRSHWroX:
case AArch64::LDRSHWui:
case AArch64::LDRSHXroW:
case AArch64::LDRSHXroX:
case AArch64::LDRSHXui:
case AArch64::LDRSWl:
case AArch64::LDRSWroW:
case AArch64::LDRSWroX:
case AArch64::LDRSWui:
case AArch64::LDRSl:
case AArch64::LDRSroW:
case AArch64::LDRSroX:
case AArch64::LDRSui:
case AArch64::LDRWl:
case AArch64::LDRWroW:
case AArch64::LDRWroX:
case AArch64::LDRWui:
case AArch64::LDRXl:
case AArch64::LDRXroW:
case AArch64::LDRXroX:
case AArch64::LDRXui:
case AArch64::LDURBBi:
case AArch64::LDURBi:
case AArch64::LDURDi:
case AArch64::LDURHHi:
case AArch64::LDURHi:
case AArch64::LDURQi:
case AArch64::LDURSBWi:
case AArch64::LDURSBXi:
case AArch64::LDURSHWi:
case AArch64::LDURSHXi:
case AArch64::LDURSWi:
case AArch64::LDURSi:
case AArch64::LDURWi:
case AArch64::LDURXi:
DestRegIdx = 0;
BaseRegIdx = 1;
OffsetIdx = 2;
IsPrePost = false;
break;
case AArch64::LDRBBpost:
case AArch64::LDRBBpre:
case AArch64::LDRBpost:
case AArch64::LDRBpre:
case AArch64::LDRDpost:
case AArch64::LDRDpre:
case AArch64::LDRHHpost:
case AArch64::LDRHHpre:
case AArch64::LDRHpost:
case AArch64::LDRHpre:
case AArch64::LDRQpost:
case AArch64::LDRQpre:
case AArch64::LDRSBWpost:
case AArch64::LDRSBWpre:
case AArch64::LDRSBXpost:
case AArch64::LDRSBXpre:
case AArch64::LDRSHWpost:
case AArch64::LDRSHWpre:
case AArch64::LDRSHXpost:
case AArch64::LDRSHXpre:
case AArch64::LDRSWpost:
case AArch64::LDRSWpre:
case AArch64::LDRSpost:
case AArch64::LDRSpre:
case AArch64::LDRWpost:
case AArch64::LDRWpre:
case AArch64::LDRXpost:
case AArch64::LDRXpre:
DestRegIdx = 1;
BaseRegIdx = 2;
OffsetIdx = 3;
IsPrePost = true;
break;
case AArch64::LDNPDi:
case AArch64::LDNPQi:
case AArch64::LDNPSi:
case AArch64::LDPQi:
case AArch64::LDPDi:
case AArch64::LDPSi:
DestRegIdx = -1;
BaseRegIdx = 2;
OffsetIdx = 3;
IsPrePost = false;
break;
case AArch64::LDPSWi:
case AArch64::LDPWi:
case AArch64::LDPXi:
DestRegIdx = 0;
BaseRegIdx = 2;
OffsetIdx = 3;
IsPrePost = false;
break;
case AArch64::LDPQpost:
case AArch64::LDPQpre:
case AArch64::LDPDpost:
case AArch64::LDPDpre:
case AArch64::LDPSpost:
case AArch64::LDPSpre:
DestRegIdx = -1;
BaseRegIdx = 3;
OffsetIdx = 4;
IsPrePost = true;
break;
case AArch64::LDPSWpost:
case AArch64::LDPSWpre:
case AArch64::LDPWpost:
case AArch64::LDPWpre:
case AArch64::LDPXpost:
case AArch64::LDPXpre:
DestRegIdx = 1;
BaseRegIdx = 3;
OffsetIdx = 4;
IsPrePost = true;
break;
}
// Loads from the stack pointer don't get prefetched.
Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
if (BaseReg == AArch64::SP || BaseReg == AArch64::WSP)
return None;
LoadInfo LI;
LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();
LI.BaseReg = BaseReg;
LI.BaseRegIdx = BaseRegIdx;
LI.OffsetOpnd = OffsetIdx == -1 ? nullptr : &MI.getOperand(OffsetIdx);
LI.IsPrePost = IsPrePost;
return LI;
}