in llvm/lib/Target/X86/X86InstrInfo.cpp [8385:8701]
bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
switch (Inst.getOpcode()) {
case X86::AND8rr:
case X86::AND16rr:
case X86::AND32rr:
case X86::AND64rr:
case X86::OR8rr:
case X86::OR16rr:
case X86::OR32rr:
case X86::OR64rr:
case X86::XOR8rr:
case X86::XOR16rr:
case X86::XOR32rr:
case X86::XOR64rr:
case X86::IMUL16rr:
case X86::IMUL32rr:
case X86::IMUL64rr:
case X86::PANDrr:
case X86::PORrr:
case X86::PXORrr:
case X86::ANDPDrr:
case X86::ANDPSrr:
case X86::ORPDrr:
case X86::ORPSrr:
case X86::XORPDrr:
case X86::XORPSrr:
case X86::PADDBrr:
case X86::PADDWrr:
case X86::PADDDrr:
case X86::PADDQrr:
case X86::PMULLWrr:
case X86::PMULLDrr:
case X86::PMAXSBrr:
case X86::PMAXSDrr:
case X86::PMAXSWrr:
case X86::PMAXUBrr:
case X86::PMAXUDrr:
case X86::PMAXUWrr:
case X86::PMINSBrr:
case X86::PMINSDrr:
case X86::PMINSWrr:
case X86::PMINUBrr:
case X86::PMINUDrr:
case X86::PMINUWrr:
case X86::VPANDrr:
case X86::VPANDYrr:
case X86::VPANDDZ128rr:
case X86::VPANDDZ256rr:
case X86::VPANDDZrr:
case X86::VPANDQZ128rr:
case X86::VPANDQZ256rr:
case X86::VPANDQZrr:
case X86::VPORrr:
case X86::VPORYrr:
case X86::VPORDZ128rr:
case X86::VPORDZ256rr:
case X86::VPORDZrr:
case X86::VPORQZ128rr:
case X86::VPORQZ256rr:
case X86::VPORQZrr:
case X86::VPXORrr:
case X86::VPXORYrr:
case X86::VPXORDZ128rr:
case X86::VPXORDZ256rr:
case X86::VPXORDZrr:
case X86::VPXORQZ128rr:
case X86::VPXORQZ256rr:
case X86::VPXORQZrr:
case X86::VANDPDrr:
case X86::VANDPSrr:
case X86::VANDPDYrr:
case X86::VANDPSYrr:
case X86::VANDPDZ128rr:
case X86::VANDPSZ128rr:
case X86::VANDPDZ256rr:
case X86::VANDPSZ256rr:
case X86::VANDPDZrr:
case X86::VANDPSZrr:
case X86::VORPDrr:
case X86::VORPSrr:
case X86::VORPDYrr:
case X86::VORPSYrr:
case X86::VORPDZ128rr:
case X86::VORPSZ128rr:
case X86::VORPDZ256rr:
case X86::VORPSZ256rr:
case X86::VORPDZrr:
case X86::VORPSZrr:
case X86::VXORPDrr:
case X86::VXORPSrr:
case X86::VXORPDYrr:
case X86::VXORPSYrr:
case X86::VXORPDZ128rr:
case X86::VXORPSZ128rr:
case X86::VXORPDZ256rr:
case X86::VXORPSZ256rr:
case X86::VXORPDZrr:
case X86::VXORPSZrr:
case X86::KADDBrr:
case X86::KADDWrr:
case X86::KADDDrr:
case X86::KADDQrr:
case X86::KANDBrr:
case X86::KANDWrr:
case X86::KANDDrr:
case X86::KANDQrr:
case X86::KORBrr:
case X86::KORWrr:
case X86::KORDrr:
case X86::KORQrr:
case X86::KXORBrr:
case X86::KXORWrr:
case X86::KXORDrr:
case X86::KXORQrr:
case X86::VPADDBrr:
case X86::VPADDWrr:
case X86::VPADDDrr:
case X86::VPADDQrr:
case X86::VPADDBYrr:
case X86::VPADDWYrr:
case X86::VPADDDYrr:
case X86::VPADDQYrr:
case X86::VPADDBZ128rr:
case X86::VPADDWZ128rr:
case X86::VPADDDZ128rr:
case X86::VPADDQZ128rr:
case X86::VPADDBZ256rr:
case X86::VPADDWZ256rr:
case X86::VPADDDZ256rr:
case X86::VPADDQZ256rr:
case X86::VPADDBZrr:
case X86::VPADDWZrr:
case X86::VPADDDZrr:
case X86::VPADDQZrr:
case X86::VPMULLWrr:
case X86::VPMULLWYrr:
case X86::VPMULLWZ128rr:
case X86::VPMULLWZ256rr:
case X86::VPMULLWZrr:
case X86::VPMULLDrr:
case X86::VPMULLDYrr:
case X86::VPMULLDZ128rr:
case X86::VPMULLDZ256rr:
case X86::VPMULLDZrr:
case X86::VPMULLQZ128rr:
case X86::VPMULLQZ256rr:
case X86::VPMULLQZrr:
case X86::VPMAXSBrr:
case X86::VPMAXSBYrr:
case X86::VPMAXSBZ128rr:
case X86::VPMAXSBZ256rr:
case X86::VPMAXSBZrr:
case X86::VPMAXSDrr:
case X86::VPMAXSDYrr:
case X86::VPMAXSDZ128rr:
case X86::VPMAXSDZ256rr:
case X86::VPMAXSDZrr:
case X86::VPMAXSQZ128rr:
case X86::VPMAXSQZ256rr:
case X86::VPMAXSQZrr:
case X86::VPMAXSWrr:
case X86::VPMAXSWYrr:
case X86::VPMAXSWZ128rr:
case X86::VPMAXSWZ256rr:
case X86::VPMAXSWZrr:
case X86::VPMAXUBrr:
case X86::VPMAXUBYrr:
case X86::VPMAXUBZ128rr:
case X86::VPMAXUBZ256rr:
case X86::VPMAXUBZrr:
case X86::VPMAXUDrr:
case X86::VPMAXUDYrr:
case X86::VPMAXUDZ128rr:
case X86::VPMAXUDZ256rr:
case X86::VPMAXUDZrr:
case X86::VPMAXUQZ128rr:
case X86::VPMAXUQZ256rr:
case X86::VPMAXUQZrr:
case X86::VPMAXUWrr:
case X86::VPMAXUWYrr:
case X86::VPMAXUWZ128rr:
case X86::VPMAXUWZ256rr:
case X86::VPMAXUWZrr:
case X86::VPMINSBrr:
case X86::VPMINSBYrr:
case X86::VPMINSBZ128rr:
case X86::VPMINSBZ256rr:
case X86::VPMINSBZrr:
case X86::VPMINSDrr:
case X86::VPMINSDYrr:
case X86::VPMINSDZ128rr:
case X86::VPMINSDZ256rr:
case X86::VPMINSDZrr:
case X86::VPMINSQZ128rr:
case X86::VPMINSQZ256rr:
case X86::VPMINSQZrr:
case X86::VPMINSWrr:
case X86::VPMINSWYrr:
case X86::VPMINSWZ128rr:
case X86::VPMINSWZ256rr:
case X86::VPMINSWZrr:
case X86::VPMINUBrr:
case X86::VPMINUBYrr:
case X86::VPMINUBZ128rr:
case X86::VPMINUBZ256rr:
case X86::VPMINUBZrr:
case X86::VPMINUDrr:
case X86::VPMINUDYrr:
case X86::VPMINUDZ128rr:
case X86::VPMINUDZ256rr:
case X86::VPMINUDZrr:
case X86::VPMINUQZ128rr:
case X86::VPMINUQZ256rr:
case X86::VPMINUQZrr:
case X86::VPMINUWrr:
case X86::VPMINUWYrr:
case X86::VPMINUWZ128rr:
case X86::VPMINUWZ256rr:
case X86::VPMINUWZrr:
// Normal min/max instructions are not commutative because of NaN and signed
// zero semantics, but these are. Thus, there's no need to check for global
// relaxed math; the instructions themselves have the properties we need.
case X86::MAXCPDrr:
case X86::MAXCPSrr:
case X86::MAXCSDrr:
case X86::MAXCSSrr:
case X86::MINCPDrr:
case X86::MINCPSrr:
case X86::MINCSDrr:
case X86::MINCSSrr:
case X86::VMAXCPDrr:
case X86::VMAXCPSrr:
case X86::VMAXCPDYrr:
case X86::VMAXCPSYrr:
case X86::VMAXCPDZ128rr:
case X86::VMAXCPSZ128rr:
case X86::VMAXCPDZ256rr:
case X86::VMAXCPSZ256rr:
case X86::VMAXCPDZrr:
case X86::VMAXCPSZrr:
case X86::VMAXCSDrr:
case X86::VMAXCSSrr:
case X86::VMAXCSDZrr:
case X86::VMAXCSSZrr:
case X86::VMINCPDrr:
case X86::VMINCPSrr:
case X86::VMINCPDYrr:
case X86::VMINCPSYrr:
case X86::VMINCPDZ128rr:
case X86::VMINCPSZ128rr:
case X86::VMINCPDZ256rr:
case X86::VMINCPSZ256rr:
case X86::VMINCPDZrr:
case X86::VMINCPSZrr:
case X86::VMINCSDrr:
case X86::VMINCSSrr:
case X86::VMINCSDZrr:
case X86::VMINCSSZrr:
case X86::VMAXCPHZ128rr:
case X86::VMAXCPHZ256rr:
case X86::VMAXCPHZrr:
case X86::VMAXCSHZrr:
case X86::VMINCPHZ128rr:
case X86::VMINCPHZ256rr:
case X86::VMINCPHZrr:
case X86::VMINCSHZrr:
return true;
case X86::ADDPDrr:
case X86::ADDPSrr:
case X86::ADDSDrr:
case X86::ADDSSrr:
case X86::MULPDrr:
case X86::MULPSrr:
case X86::MULSDrr:
case X86::MULSSrr:
case X86::VADDPDrr:
case X86::VADDPSrr:
case X86::VADDPDYrr:
case X86::VADDPSYrr:
case X86::VADDPDZ128rr:
case X86::VADDPSZ128rr:
case X86::VADDPDZ256rr:
case X86::VADDPSZ256rr:
case X86::VADDPDZrr:
case X86::VADDPSZrr:
case X86::VADDSDrr:
case X86::VADDSSrr:
case X86::VADDSDZrr:
case X86::VADDSSZrr:
case X86::VMULPDrr:
case X86::VMULPSrr:
case X86::VMULPDYrr:
case X86::VMULPSYrr:
case X86::VMULPDZ128rr:
case X86::VMULPSZ128rr:
case X86::VMULPDZ256rr:
case X86::VMULPSZ256rr:
case X86::VMULPDZrr:
case X86::VMULPSZrr:
case X86::VMULSDrr:
case X86::VMULSSrr:
case X86::VMULSDZrr:
case X86::VMULSSZrr:
case X86::VADDPHZ128rr:
case X86::VADDPHZ256rr:
case X86::VADDPHZrr:
case X86::VADDSHZrr:
case X86::VMULPHZ128rr:
case X86::VMULPHZ256rr:
case X86::VMULPHZrr:
case X86::VMULSHZrr:
return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
Inst.getFlag(MachineInstr::MIFlag::FmNsz);
default:
return false;
}
}