in llvm/lib/Target/X86/X86InstrInfo.cpp [5155:5481]
static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
bool ForLoadFold = false) {
// Set the OpNum parameter to the first source operand.
switch (Opcode) {
case X86::MMX_PUNPCKHBWrr:
case X86::MMX_PUNPCKHWDrr:
case X86::MMX_PUNPCKHDQrr:
case X86::MMX_PUNPCKLBWrr:
case X86::MMX_PUNPCKLWDrr:
case X86::MMX_PUNPCKLDQrr:
case X86::MOVHLPSrr:
case X86::PACKSSWBrr:
case X86::PACKUSWBrr:
case X86::PACKSSDWrr:
case X86::PACKUSDWrr:
case X86::PUNPCKHBWrr:
case X86::PUNPCKLBWrr:
case X86::PUNPCKHWDrr:
case X86::PUNPCKLWDrr:
case X86::PUNPCKHDQrr:
case X86::PUNPCKLDQrr:
case X86::PUNPCKHQDQrr:
case X86::PUNPCKLQDQrr:
case X86::SHUFPDrri:
case X86::SHUFPSrri:
// These instructions are sometimes used with an undef first or second
// source. Return true here so BreakFalseDeps will assign this source to the
// same register as the first source to avoid a false dependency.
// Operand 1 of these instructions is tied so they're separate from their
// VEX counterparts.
return OpNum == 2 && !ForLoadFold;
case X86::VMOVLHPSrr:
case X86::VMOVLHPSZrr:
case X86::VPACKSSWBrr:
case X86::VPACKUSWBrr:
case X86::VPACKSSDWrr:
case X86::VPACKUSDWrr:
case X86::VPACKSSWBZ128rr:
case X86::VPACKUSWBZ128rr:
case X86::VPACKSSDWZ128rr:
case X86::VPACKUSDWZ128rr:
case X86::VPERM2F128rr:
case X86::VPERM2I128rr:
case X86::VSHUFF32X4Z256rri:
case X86::VSHUFF32X4Zrri:
case X86::VSHUFF64X2Z256rri:
case X86::VSHUFF64X2Zrri:
case X86::VSHUFI32X4Z256rri:
case X86::VSHUFI32X4Zrri:
case X86::VSHUFI64X2Z256rri:
case X86::VSHUFI64X2Zrri:
case X86::VPUNPCKHBWrr:
case X86::VPUNPCKLBWrr:
case X86::VPUNPCKHBWYrr:
case X86::VPUNPCKLBWYrr:
case X86::VPUNPCKHBWZ128rr:
case X86::VPUNPCKLBWZ128rr:
case X86::VPUNPCKHBWZ256rr:
case X86::VPUNPCKLBWZ256rr:
case X86::VPUNPCKHBWZrr:
case X86::VPUNPCKLBWZrr:
case X86::VPUNPCKHWDrr:
case X86::VPUNPCKLWDrr:
case X86::VPUNPCKHWDYrr:
case X86::VPUNPCKLWDYrr:
case X86::VPUNPCKHWDZ128rr:
case X86::VPUNPCKLWDZ128rr:
case X86::VPUNPCKHWDZ256rr:
case X86::VPUNPCKLWDZ256rr:
case X86::VPUNPCKHWDZrr:
case X86::VPUNPCKLWDZrr:
case X86::VPUNPCKHDQrr:
case X86::VPUNPCKLDQrr:
case X86::VPUNPCKHDQYrr:
case X86::VPUNPCKLDQYrr:
case X86::VPUNPCKHDQZ128rr:
case X86::VPUNPCKLDQZ128rr:
case X86::VPUNPCKHDQZ256rr:
case X86::VPUNPCKLDQZ256rr:
case X86::VPUNPCKHDQZrr:
case X86::VPUNPCKLDQZrr:
case X86::VPUNPCKHQDQrr:
case X86::VPUNPCKLQDQrr:
case X86::VPUNPCKHQDQYrr:
case X86::VPUNPCKLQDQYrr:
case X86::VPUNPCKHQDQZ128rr:
case X86::VPUNPCKLQDQZ128rr:
case X86::VPUNPCKHQDQZ256rr:
case X86::VPUNPCKLQDQZ256rr:
case X86::VPUNPCKHQDQZrr:
case X86::VPUNPCKLQDQZrr:
// These instructions are sometimes used with an undef first or second
// source. Return true here so BreakFalseDeps will assign this source to the
// same register as the first source to avoid a false dependency.
return (OpNum == 1 || OpNum == 2) && !ForLoadFold;
case X86::VCVTSI2SSrr:
case X86::VCVTSI2SSrm:
case X86::VCVTSI2SSrr_Int:
case X86::VCVTSI2SSrm_Int:
case X86::VCVTSI642SSrr:
case X86::VCVTSI642SSrm:
case X86::VCVTSI642SSrr_Int:
case X86::VCVTSI642SSrm_Int:
case X86::VCVTSI2SDrr:
case X86::VCVTSI2SDrm:
case X86::VCVTSI2SDrr_Int:
case X86::VCVTSI2SDrm_Int:
case X86::VCVTSI642SDrr:
case X86::VCVTSI642SDrm:
case X86::VCVTSI642SDrr_Int:
case X86::VCVTSI642SDrm_Int:
// AVX-512
case X86::VCVTSI2SSZrr:
case X86::VCVTSI2SSZrm:
case X86::VCVTSI2SSZrr_Int:
case X86::VCVTSI2SSZrrb_Int:
case X86::VCVTSI2SSZrm_Int:
case X86::VCVTSI642SSZrr:
case X86::VCVTSI642SSZrm:
case X86::VCVTSI642SSZrr_Int:
case X86::VCVTSI642SSZrrb_Int:
case X86::VCVTSI642SSZrm_Int:
case X86::VCVTSI2SDZrr:
case X86::VCVTSI2SDZrm:
case X86::VCVTSI2SDZrr_Int:
case X86::VCVTSI2SDZrm_Int:
case X86::VCVTSI642SDZrr:
case X86::VCVTSI642SDZrm:
case X86::VCVTSI642SDZrr_Int:
case X86::VCVTSI642SDZrrb_Int:
case X86::VCVTSI642SDZrm_Int:
case X86::VCVTUSI2SSZrr:
case X86::VCVTUSI2SSZrm:
case X86::VCVTUSI2SSZrr_Int:
case X86::VCVTUSI2SSZrrb_Int:
case X86::VCVTUSI2SSZrm_Int:
case X86::VCVTUSI642SSZrr:
case X86::VCVTUSI642SSZrm:
case X86::VCVTUSI642SSZrr_Int:
case X86::VCVTUSI642SSZrrb_Int:
case X86::VCVTUSI642SSZrm_Int:
case X86::VCVTUSI2SDZrr:
case X86::VCVTUSI2SDZrm:
case X86::VCVTUSI2SDZrr_Int:
case X86::VCVTUSI2SDZrm_Int:
case X86::VCVTUSI642SDZrr:
case X86::VCVTUSI642SDZrm:
case X86::VCVTUSI642SDZrr_Int:
case X86::VCVTUSI642SDZrrb_Int:
case X86::VCVTUSI642SDZrm_Int:
case X86::VCVTSI2SHZrr:
case X86::VCVTSI2SHZrm:
case X86::VCVTSI2SHZrr_Int:
case X86::VCVTSI2SHZrrb_Int:
case X86::VCVTSI2SHZrm_Int:
case X86::VCVTSI642SHZrr:
case X86::VCVTSI642SHZrm:
case X86::VCVTSI642SHZrr_Int:
case X86::VCVTSI642SHZrrb_Int:
case X86::VCVTSI642SHZrm_Int:
case X86::VCVTUSI2SHZrr:
case X86::VCVTUSI2SHZrm:
case X86::VCVTUSI2SHZrr_Int:
case X86::VCVTUSI2SHZrrb_Int:
case X86::VCVTUSI2SHZrm_Int:
case X86::VCVTUSI642SHZrr:
case X86::VCVTUSI642SHZrm:
case X86::VCVTUSI642SHZrr_Int:
case X86::VCVTUSI642SHZrrb_Int:
case X86::VCVTUSI642SHZrm_Int:
// Load folding won't effect the undef register update since the input is
// a GPR.
return OpNum == 1 && !ForLoadFold;
case X86::VCVTSD2SSrr:
case X86::VCVTSD2SSrm:
case X86::VCVTSD2SSrr_Int:
case X86::VCVTSD2SSrm_Int:
case X86::VCVTSS2SDrr:
case X86::VCVTSS2SDrm:
case X86::VCVTSS2SDrr_Int:
case X86::VCVTSS2SDrm_Int:
case X86::VRCPSSr:
case X86::VRCPSSr_Int:
case X86::VRCPSSm:
case X86::VRCPSSm_Int:
case X86::VROUNDSDr:
case X86::VROUNDSDm:
case X86::VROUNDSDr_Int:
case X86::VROUNDSDm_Int:
case X86::VROUNDSSr:
case X86::VROUNDSSm:
case X86::VROUNDSSr_Int:
case X86::VROUNDSSm_Int:
case X86::VRSQRTSSr:
case X86::VRSQRTSSr_Int:
case X86::VRSQRTSSm:
case X86::VRSQRTSSm_Int:
case X86::VSQRTSSr:
case X86::VSQRTSSr_Int:
case X86::VSQRTSSm:
case X86::VSQRTSSm_Int:
case X86::VSQRTSDr:
case X86::VSQRTSDr_Int:
case X86::VSQRTSDm:
case X86::VSQRTSDm_Int:
// AVX-512
case X86::VCVTSD2SSZrr:
case X86::VCVTSD2SSZrr_Int:
case X86::VCVTSD2SSZrrb_Int:
case X86::VCVTSD2SSZrm:
case X86::VCVTSD2SSZrm_Int:
case X86::VCVTSS2SDZrr:
case X86::VCVTSS2SDZrr_Int:
case X86::VCVTSS2SDZrrb_Int:
case X86::VCVTSS2SDZrm:
case X86::VCVTSS2SDZrm_Int:
case X86::VGETEXPSDZr:
case X86::VGETEXPSDZrb:
case X86::VGETEXPSDZm:
case X86::VGETEXPSSZr:
case X86::VGETEXPSSZrb:
case X86::VGETEXPSSZm:
case X86::VGETMANTSDZrri:
case X86::VGETMANTSDZrrib:
case X86::VGETMANTSDZrmi:
case X86::VGETMANTSSZrri:
case X86::VGETMANTSSZrrib:
case X86::VGETMANTSSZrmi:
case X86::VRNDSCALESDZr:
case X86::VRNDSCALESDZr_Int:
case X86::VRNDSCALESDZrb_Int:
case X86::VRNDSCALESDZm:
case X86::VRNDSCALESDZm_Int:
case X86::VRNDSCALESSZr:
case X86::VRNDSCALESSZr_Int:
case X86::VRNDSCALESSZrb_Int:
case X86::VRNDSCALESSZm:
case X86::VRNDSCALESSZm_Int:
case X86::VRCP14SDZrr:
case X86::VRCP14SDZrm:
case X86::VRCP14SSZrr:
case X86::VRCP14SSZrm:
case X86::VRCPSHZrr:
case X86::VRCPSHZrm:
case X86::VRSQRTSHZrr:
case X86::VRSQRTSHZrm:
case X86::VREDUCESHZrmi:
case X86::VREDUCESHZrri:
case X86::VREDUCESHZrrib:
case X86::VGETEXPSHZr:
case X86::VGETEXPSHZrb:
case X86::VGETEXPSHZm:
case X86::VGETMANTSHZrri:
case X86::VGETMANTSHZrrib:
case X86::VGETMANTSHZrmi:
case X86::VRNDSCALESHZr:
case X86::VRNDSCALESHZr_Int:
case X86::VRNDSCALESHZrb_Int:
case X86::VRNDSCALESHZm:
case X86::VRNDSCALESHZm_Int:
case X86::VSQRTSHZr:
case X86::VSQRTSHZr_Int:
case X86::VSQRTSHZrb_Int:
case X86::VSQRTSHZm:
case X86::VSQRTSHZm_Int:
case X86::VRCP28SDZr:
case X86::VRCP28SDZrb:
case X86::VRCP28SDZm:
case X86::VRCP28SSZr:
case X86::VRCP28SSZrb:
case X86::VRCP28SSZm:
case X86::VREDUCESSZrmi:
case X86::VREDUCESSZrri:
case X86::VREDUCESSZrrib:
case X86::VRSQRT14SDZrr:
case X86::VRSQRT14SDZrm:
case X86::VRSQRT14SSZrr:
case X86::VRSQRT14SSZrm:
case X86::VRSQRT28SDZr:
case X86::VRSQRT28SDZrb:
case X86::VRSQRT28SDZm:
case X86::VRSQRT28SSZr:
case X86::VRSQRT28SSZrb:
case X86::VRSQRT28SSZm:
case X86::VSQRTSSZr:
case X86::VSQRTSSZr_Int:
case X86::VSQRTSSZrb_Int:
case X86::VSQRTSSZm:
case X86::VSQRTSSZm_Int:
case X86::VSQRTSDZr:
case X86::VSQRTSDZr_Int:
case X86::VSQRTSDZrb_Int:
case X86::VSQRTSDZm:
case X86::VSQRTSDZm_Int:
case X86::VCVTSD2SHZrr:
case X86::VCVTSD2SHZrr_Int:
case X86::VCVTSD2SHZrrb_Int:
case X86::VCVTSD2SHZrm:
case X86::VCVTSD2SHZrm_Int:
case X86::VCVTSS2SHZrr:
case X86::VCVTSS2SHZrr_Int:
case X86::VCVTSS2SHZrrb_Int:
case X86::VCVTSS2SHZrm:
case X86::VCVTSS2SHZrm_Int:
case X86::VCVTSH2SDZrr:
case X86::VCVTSH2SDZrr_Int:
case X86::VCVTSH2SDZrrb_Int:
case X86::VCVTSH2SDZrm:
case X86::VCVTSH2SDZrm_Int:
case X86::VCVTSH2SSZrr:
case X86::VCVTSH2SSZrr_Int:
case X86::VCVTSH2SSZrrb_Int:
case X86::VCVTSH2SSZrm:
case X86::VCVTSH2SSZrm_Int:
return OpNum == 1;
case X86::VMOVSSZrrk:
case X86::VMOVSDZrrk:
return OpNum == 3 && !ForLoadFold;
case X86::VMOVSSZrrkz:
case X86::VMOVSDZrrkz:
return OpNum == 2 && !ForLoadFold;
}
return false;
}