in disas/riscv.c [1417:2116]
static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
{
rv_inst inst = dec->inst;
rv_opcode op = rv_op_illegal;
switch (((inst >> 0) & 0b11)) {
case 0:
switch (((inst >> 13) & 0b111)) {
case 0: op = rv_op_c_addi4spn; break;
case 1:
if (isa == rv128) {
op = rv_op_c_lq;
} else {
op = rv_op_c_fld;
}
break;
case 2: op = rv_op_c_lw; break;
case 3:
if (isa == rv32) {
op = rv_op_c_flw;
} else {
op = rv_op_c_ld;
}
break;
case 5:
if (isa == rv128) {
op = rv_op_c_sq;
} else {
op = rv_op_c_fsd;
}
break;
case 6: op = rv_op_c_sw; break;
case 7:
if (isa == rv32) {
op = rv_op_c_fsw;
} else {
op = rv_op_c_sd;
}
break;
}
break;
case 1:
switch (((inst >> 13) & 0b111)) {
case 0:
switch (((inst >> 2) & 0b11111111111)) {
case 0: op = rv_op_c_nop; break;
default: op = rv_op_c_addi; break;
}
break;
case 1:
if (isa == rv32) {
op = rv_op_c_jal;
} else {
op = rv_op_c_addiw;
}
break;
case 2: op = rv_op_c_li; break;
case 3:
switch (((inst >> 7) & 0b11111)) {
case 2: op = rv_op_c_addi16sp; break;
default: op = rv_op_c_lui; break;
}
break;
case 4:
switch (((inst >> 10) & 0b11)) {
case 0:
op = rv_op_c_srli;
break;
case 1:
op = rv_op_c_srai;
break;
case 2: op = rv_op_c_andi; break;
case 3:
switch (((inst >> 10) & 0b100) | ((inst >> 5) & 0b011)) {
case 0: op = rv_op_c_sub; break;
case 1: op = rv_op_c_xor; break;
case 2: op = rv_op_c_or; break;
case 3: op = rv_op_c_and; break;
case 4: op = rv_op_c_subw; break;
case 5: op = rv_op_c_addw; break;
}
break;
}
break;
case 5: op = rv_op_c_j; break;
case 6: op = rv_op_c_beqz; break;
case 7: op = rv_op_c_bnez; break;
}
break;
case 2:
switch (((inst >> 13) & 0b111)) {
case 0:
op = rv_op_c_slli;
break;
case 1:
if (isa == rv128) {
op = rv_op_c_lqsp;
} else {
op = rv_op_c_fldsp;
}
break;
case 2: op = rv_op_c_lwsp; break;
case 3:
if (isa == rv32) {
op = rv_op_c_flwsp;
} else {
op = rv_op_c_ldsp;
}
break;
case 4:
switch (((inst >> 12) & 0b1)) {
case 0:
switch (((inst >> 2) & 0b11111)) {
case 0: op = rv_op_c_jr; break;
default: op = rv_op_c_mv; break;
}
break;
case 1:
switch (((inst >> 2) & 0b11111)) {
case 0:
switch (((inst >> 7) & 0b11111)) {
case 0: op = rv_op_c_ebreak; break;
default: op = rv_op_c_jalr; break;
}
break;
default: op = rv_op_c_add; break;
}
break;
}
break;
case 5:
if (isa == rv128) {
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
}
break;
case 6: op = rv_op_c_swsp; break;
case 7:
if (isa == rv32) {
op = rv_op_c_fswsp;
} else {
op = rv_op_c_sdsp;
}
break;
}
break;
case 3:
switch (((inst >> 2) & 0b11111)) {
case 0:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_lb; break;
case 1: op = rv_op_lh; break;
case 2: op = rv_op_lw; break;
case 3: op = rv_op_ld; break;
case 4: op = rv_op_lbu; break;
case 5: op = rv_op_lhu; break;
case 6: op = rv_op_lwu; break;
case 7: op = rv_op_ldu; break;
}
break;
case 1:
switch (((inst >> 12) & 0b111)) {
case 2: op = rv_op_flw; break;
case 3: op = rv_op_fld; break;
case 4: op = rv_op_flq; break;
}
break;
case 3:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fence; break;
case 1: op = rv_op_fence_i; break;
case 2: op = rv_op_lq; break;
}
break;
case 4:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_addi; break;
case 1:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_slli; break;
case 0b00101: op = rv_op_bseti; break;
case 0b01001: op = rv_op_bclri; break;
case 0b01101: op = rv_op_binvi; break;
case 0b01100:
switch (((inst >> 20) & 0b1111111)) {
case 0b0000000: op = rv_op_clz; break;
case 0b0000001: op = rv_op_ctz; break;
case 0b0000010: op = rv_op_cpop; break;
/* 0b0000011 */
case 0b0000100: op = rv_op_sext_b; break;
case 0b0000101: op = rv_op_sext_h; break;
}
break;
}
break;
case 2: op = rv_op_slti; break;
case 3: op = rv_op_sltiu; break;
case 4: op = rv_op_xori; break;
case 5:
switch (((inst >> 27) & 0b11111)) {
case 0b00000: op = rv_op_srli; break;
case 0b00101: op = rv_op_orc_b; break;
case 0b01000: op = rv_op_srai; break;
case 0b01001: op = rv_op_bexti; break;
case 0b01100: op = rv_op_rori; break;
case 0b01101:
switch ((inst >> 20) & 0b1111111) {
case 0b0111000: op = rv_op_rev8; break;
}
break;
}
break;
case 6: op = rv_op_ori; break;
case 7: op = rv_op_andi; break;
}
break;
case 5: op = rv_op_auipc; break;
case 6:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_addiw; break;
case 1:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_slliw; break;
case 4: op = rv_op_slli_uw; break;
case 48:
switch ((inst >> 20) & 0b11111) {
case 0b00000: op = rv_op_clzw; break;
case 0b00001: op = rv_op_ctzw; break;
case 0b00010: op = rv_op_cpopw; break;
}
break;
}
break;
case 5:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_srliw; break;
case 32: op = rv_op_sraiw; break;
case 48: op = rv_op_roriw; break;
}
break;
}
break;
case 8:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_sb; break;
case 1: op = rv_op_sh; break;
case 2: op = rv_op_sw; break;
case 3: op = rv_op_sd; break;
case 4: op = rv_op_sq; break;
}
break;
case 9:
switch (((inst >> 12) & 0b111)) {
case 2: op = rv_op_fsw; break;
case 3: op = rv_op_fsd; break;
case 4: op = rv_op_fsq; break;
}
break;
case 11:
switch (((inst >> 24) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 2: op = rv_op_amoadd_w; break;
case 3: op = rv_op_amoadd_d; break;
case 4: op = rv_op_amoadd_q; break;
case 10: op = rv_op_amoswap_w; break;
case 11: op = rv_op_amoswap_d; break;
case 12: op = rv_op_amoswap_q; break;
case 18:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_lr_w; break;
}
break;
case 19:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_lr_d; break;
}
break;
case 20:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_lr_q; break;
}
break;
case 26: op = rv_op_sc_w; break;
case 27: op = rv_op_sc_d; break;
case 28: op = rv_op_sc_q; break;
case 34: op = rv_op_amoxor_w; break;
case 35: op = rv_op_amoxor_d; break;
case 36: op = rv_op_amoxor_q; break;
case 66: op = rv_op_amoor_w; break;
case 67: op = rv_op_amoor_d; break;
case 68: op = rv_op_amoor_q; break;
case 98: op = rv_op_amoand_w; break;
case 99: op = rv_op_amoand_d; break;
case 100: op = rv_op_amoand_q; break;
case 130: op = rv_op_amomin_w; break;
case 131: op = rv_op_amomin_d; break;
case 132: op = rv_op_amomin_q; break;
case 162: op = rv_op_amomax_w; break;
case 163: op = rv_op_amomax_d; break;
case 164: op = rv_op_amomax_q; break;
case 194: op = rv_op_amominu_w; break;
case 195: op = rv_op_amominu_d; break;
case 196: op = rv_op_amominu_q; break;
case 226: op = rv_op_amomaxu_w; break;
case 227: op = rv_op_amomaxu_d; break;
case 228: op = rv_op_amomaxu_q; break;
}
break;
case 12:
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_add; break;
case 1: op = rv_op_sll; break;
case 2: op = rv_op_slt; break;
case 3: op = rv_op_sltu; break;
case 4: op = rv_op_xor; break;
case 5: op = rv_op_srl; break;
case 6: op = rv_op_or; break;
case 7: op = rv_op_and; break;
case 8: op = rv_op_mul; break;
case 9: op = rv_op_mulh; break;
case 10: op = rv_op_mulhsu; break;
case 11: op = rv_op_mulhu; break;
case 12: op = rv_op_div; break;
case 13: op = rv_op_divu; break;
case 14: op = rv_op_rem; break;
case 15: op = rv_op_remu; break;
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
}
break;
case 41: op = rv_op_clmul; break;
case 42: op = rv_op_clmulr; break;
case 43: op = rv_op_clmulh; break;
case 44: op = rv_op_min; break;
case 45: op = rv_op_minu; break;
case 46: op = rv_op_max; break;
case 47: op = rv_op_maxu; break;
case 130: op = rv_op_sh1add; break;
case 132: op = rv_op_sh2add; break;
case 134: op = rv_op_sh3add; break;
case 161: op = rv_op_bset; break;
case 256: op = rv_op_sub; break;
case 260: op = rv_op_xnor; break;
case 261: op = rv_op_sra; break;
case 262: op = rv_op_orn; break;
case 263: op = rv_op_andn; break;
case 289: op = rv_op_bclr; break;
case 293: op = rv_op_bext; break;
case 385: op = rv_op_rol; break;
case 386: op = rv_op_ror; break;
case 417: op = rv_op_binv; break;
}
break;
case 13: op = rv_op_lui; break;
case 14:
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addw; break;
case 1: op = rv_op_sllw; break;
case 5: op = rv_op_srlw; break;
case 8: op = rv_op_mulw; break;
case 12: op = rv_op_divw; break;
case 13: op = rv_op_divuw; break;
case 14: op = rv_op_remw; break;
case 15: op = rv_op_remuw; break;
case 32: op = rv_op_add_uw; break;
case 36:
switch ((inst >> 20) & 0b11111) {
case 0: op = rv_op_zext_h; break;
}
break;
case 130: op = rv_op_sh1add_uw; break;
case 132: op = rv_op_sh2add_uw; break;
case 134: op = rv_op_sh3add_uw; break;
case 256: op = rv_op_subw; break;
case 261: op = rv_op_sraw; break;
case 385: op = rv_op_rolw; break;
case 389: op = rv_op_rorw; break;
}
break;
case 16:
switch (((inst >> 25) & 0b11)) {
case 0: op = rv_op_fmadd_s; break;
case 1: op = rv_op_fmadd_d; break;
case 3: op = rv_op_fmadd_q; break;
}
break;
case 17:
switch (((inst >> 25) & 0b11)) {
case 0: op = rv_op_fmsub_s; break;
case 1: op = rv_op_fmsub_d; break;
case 3: op = rv_op_fmsub_q; break;
}
break;
case 18:
switch (((inst >> 25) & 0b11)) {
case 0: op = rv_op_fnmsub_s; break;
case 1: op = rv_op_fnmsub_d; break;
case 3: op = rv_op_fnmsub_q; break;
}
break;
case 19:
switch (((inst >> 25) & 0b11)) {
case 0: op = rv_op_fnmadd_s; break;
case 1: op = rv_op_fnmadd_d; break;
case 3: op = rv_op_fnmadd_q; break;
}
break;
case 20:
switch (((inst >> 25) & 0b1111111)) {
case 0: op = rv_op_fadd_s; break;
case 1: op = rv_op_fadd_d; break;
case 3: op = rv_op_fadd_q; break;
case 4: op = rv_op_fsub_s; break;
case 5: op = rv_op_fsub_d; break;
case 7: op = rv_op_fsub_q; break;
case 8: op = rv_op_fmul_s; break;
case 9: op = rv_op_fmul_d; break;
case 11: op = rv_op_fmul_q; break;
case 12: op = rv_op_fdiv_s; break;
case 13: op = rv_op_fdiv_d; break;
case 15: op = rv_op_fdiv_q; break;
case 16:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fsgnj_s; break;
case 1: op = rv_op_fsgnjn_s; break;
case 2: op = rv_op_fsgnjx_s; break;
}
break;
case 17:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fsgnj_d; break;
case 1: op = rv_op_fsgnjn_d; break;
case 2: op = rv_op_fsgnjx_d; break;
}
break;
case 19:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fsgnj_q; break;
case 1: op = rv_op_fsgnjn_q; break;
case 2: op = rv_op_fsgnjx_q; break;
}
break;
case 20:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmin_s; break;
case 1: op = rv_op_fmax_s; break;
}
break;
case 21:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmin_d; break;
case 1: op = rv_op_fmax_d; break;
}
break;
case 23:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fmin_q; break;
case 1: op = rv_op_fmax_q; break;
}
break;
case 32:
switch (((inst >> 20) & 0b11111)) {
case 1: op = rv_op_fcvt_s_d; break;
case 3: op = rv_op_fcvt_s_q; break;
}
break;
case 33:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_d_s; break;
case 3: op = rv_op_fcvt_d_q; break;
}
break;
case 35:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_q_s; break;
case 1: op = rv_op_fcvt_q_d; break;
}
break;
case 44:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fsqrt_s; break;
}
break;
case 45:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fsqrt_d; break;
}
break;
case 47:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fsqrt_q; break;
}
break;
case 80:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fle_s; break;
case 1: op = rv_op_flt_s; break;
case 2: op = rv_op_feq_s; break;
}
break;
case 81:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fle_d; break;
case 1: op = rv_op_flt_d; break;
case 2: op = rv_op_feq_d; break;
}
break;
case 83:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_fle_q; break;
case 1: op = rv_op_flt_q; break;
case 2: op = rv_op_feq_q; break;
}
break;
case 96:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_w_s; break;
case 1: op = rv_op_fcvt_wu_s; break;
case 2: op = rv_op_fcvt_l_s; break;
case 3: op = rv_op_fcvt_lu_s; break;
}
break;
case 97:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_w_d; break;
case 1: op = rv_op_fcvt_wu_d; break;
case 2: op = rv_op_fcvt_l_d; break;
case 3: op = rv_op_fcvt_lu_d; break;
}
break;
case 99:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_w_q; break;
case 1: op = rv_op_fcvt_wu_q; break;
case 2: op = rv_op_fcvt_l_q; break;
case 3: op = rv_op_fcvt_lu_q; break;
}
break;
case 104:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_s_w; break;
case 1: op = rv_op_fcvt_s_wu; break;
case 2: op = rv_op_fcvt_s_l; break;
case 3: op = rv_op_fcvt_s_lu; break;
}
break;
case 105:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_d_w; break;
case 1: op = rv_op_fcvt_d_wu; break;
case 2: op = rv_op_fcvt_d_l; break;
case 3: op = rv_op_fcvt_d_lu; break;
}
break;
case 107:
switch (((inst >> 20) & 0b11111)) {
case 0: op = rv_op_fcvt_q_w; break;
case 1: op = rv_op_fcvt_q_wu; break;
case 2: op = rv_op_fcvt_q_l; break;
case 3: op = rv_op_fcvt_q_lu; break;
}
break;
case 112:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_s; break;
case 1: op = rv_op_fclass_s; break;
}
break;
case 113:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_d; break;
case 1: op = rv_op_fclass_d; break;
}
break;
case 115:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_x_q; break;
case 1: op = rv_op_fclass_q; break;
}
break;
case 120:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_s_x; break;
}
break;
case 121:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_d_x; break;
}
break;
case 123:
switch (((inst >> 17) & 0b11111000) | ((inst >> 12) & 0b00000111)) {
case 0: op = rv_op_fmv_q_x; break;
}
break;
}
break;
case 22:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_addid; break;
case 1:
switch (((inst >> 26) & 0b111111)) {
case 0: op = rv_op_sllid; break;
}
break;
case 5:
switch (((inst >> 26) & 0b111111)) {
case 0: op = rv_op_srlid; break;
case 16: op = rv_op_sraid; break;
}
break;
}
break;
case 24:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_beq; break;
case 1: op = rv_op_bne; break;
case 4: op = rv_op_blt; break;
case 5: op = rv_op_bge; break;
case 6: op = rv_op_bltu; break;
case 7: op = rv_op_bgeu; break;
}
break;
case 25:
switch (((inst >> 12) & 0b111)) {
case 0: op = rv_op_jalr; break;
}
break;
case 27: op = rv_op_jal; break;
case 28:
switch (((inst >> 12) & 0b111)) {
case 0:
switch (((inst >> 20) & 0b111111100000) | ((inst >> 7) & 0b000000011111)) {
case 0:
switch (((inst >> 15) & 0b1111111111)) {
case 0: op = rv_op_ecall; break;
case 32: op = rv_op_ebreak; break;
case 64: op = rv_op_uret; break;
}
break;
case 256:
switch (((inst >> 20) & 0b11111)) {
case 2:
switch (((inst >> 15) & 0b11111)) {
case 0: op = rv_op_sret; break;
}
break;
case 4: op = rv_op_sfence_vm; break;
case 5:
switch (((inst >> 15) & 0b11111)) {
case 0: op = rv_op_wfi; break;
}
break;
}
break;
case 288: op = rv_op_sfence_vma; break;
case 512:
switch (((inst >> 15) & 0b1111111111)) {
case 64: op = rv_op_hret; break;
}
break;
case 768:
switch (((inst >> 15) & 0b1111111111)) {
case 64: op = rv_op_mret; break;
}
break;
case 1952:
switch (((inst >> 15) & 0b1111111111)) {
case 576: op = rv_op_dret; break;
}
break;
}
break;
case 1: op = rv_op_csrrw; break;
case 2: op = rv_op_csrrs; break;
case 3: op = rv_op_csrrc; break;
case 5: op = rv_op_csrrwi; break;
case 6: op = rv_op_csrrsi; break;
case 7: op = rv_op_csrrci; break;
}
break;
case 30:
switch (((inst >> 22) & 0b1111111000) | ((inst >> 12) & 0b0000000111)) {
case 0: op = rv_op_addd; break;
case 1: op = rv_op_slld; break;
case 5: op = rv_op_srld; break;
case 8: op = rv_op_muld; break;
case 12: op = rv_op_divd; break;
case 13: op = rv_op_divud; break;
case 14: op = rv_op_remd; break;
case 15: op = rv_op_remud; break;
case 256: op = rv_op_subd; break;
case 261: op = rv_op_srad; break;
}
break;
}
break;
}
dec->op = op;
}