in hw/display/ati.c [518:917]
static void ati_mm_write(void *opaque, hwaddr addr,
uint64_t data, unsigned int size)
{
ATIVGAState *s = opaque;
if (addr < CUR_OFFSET || addr > CUR_CLR1 || ATI_DEBUG_HW_CURSOR) {
trace_ati_mm_write(size, addr, ati_reg_name(addr & ~3ULL), data);
}
switch (addr) {
case MM_INDEX:
s->regs.mm_index = data & ~3;
break;
case MM_DATA ... MM_DATA + 3:
/* indexed access to regs or memory */
if (s->regs.mm_index & BIT(31)) {
uint32_t idx = s->regs.mm_index & ~BIT(31);
if (idx <= s->vga.vram_size - size) {
stn_le_p(s->vga.vram_ptr + idx, size, data);
}
} else if (s->regs.mm_index > MM_DATA + 3) {
ati_mm_write(s, s->regs.mm_index + addr - MM_DATA, data, size);
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ati_mm_write: mm_index too small: %u\n", s->regs.mm_index);
}
break;
case BIOS_0_SCRATCH ... BUS_CNTL - 1:
{
int i = (addr - BIOS_0_SCRATCH) / 4;
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF && i > 3) {
break;
}
ati_reg_write_offs(&s->regs.bios_scratch[i],
addr - (BIOS_0_SCRATCH + i * 4), data, size);
break;
}
case GEN_INT_CNTL:
s->regs.gen_int_cntl = data;
if (data & CRTC_VBLANK_INT) {
ati_vga_vblank_irq(s);
} else {
timer_del(&s->vblank_timer);
ati_vga_update_irq(s);
}
break;
case GEN_INT_STATUS:
data &= (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF ?
0x000f040fUL : 0xfc080effUL);
s->regs.gen_int_status &= ~data;
ati_vga_update_irq(s);
break;
case CRTC_GEN_CNTL ... CRTC_GEN_CNTL + 3:
{
uint32_t val = s->regs.crtc_gen_cntl;
ati_reg_write_offs(&s->regs.crtc_gen_cntl,
addr - CRTC_GEN_CNTL, data, size);
if ((val & CRTC2_CUR_EN) != (s->regs.crtc_gen_cntl & CRTC2_CUR_EN)) {
if (s->cursor_guest_mode) {
s->vga.force_shadow = !!(s->regs.crtc_gen_cntl & CRTC2_CUR_EN);
} else {
if (s->regs.crtc_gen_cntl & CRTC2_CUR_EN) {
ati_cursor_define(s);
}
dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
s->regs.cur_hv_pos & 0xffff,
(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) != 0);
}
}
if ((val & (CRTC2_EXT_DISP_EN | CRTC2_EN)) !=
(s->regs.crtc_gen_cntl & (CRTC2_EXT_DISP_EN | CRTC2_EN))) {
ati_vga_switch_mode(s);
}
break;
}
case CRTC_EXT_CNTL ... CRTC_EXT_CNTL + 3:
{
uint32_t val = s->regs.crtc_ext_cntl;
ati_reg_write_offs(&s->regs.crtc_ext_cntl,
addr - CRTC_EXT_CNTL, data, size);
if (s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS) {
DPRINTF("Display disabled\n");
s->vga.ar_index &= ~BIT(5);
} else {
DPRINTF("Display enabled\n");
s->vga.ar_index |= BIT(5);
ati_vga_switch_mode(s);
}
if ((val & CRT_CRTC_DISPLAY_DIS) !=
(s->regs.crtc_ext_cntl & CRT_CRTC_DISPLAY_DIS)) {
ati_vga_switch_mode(s);
}
break;
}
case DAC_CNTL:
s->regs.dac_cntl = data & 0xffffe3ff;
s->vga.dac_8bit = !!(data & DAC_8BIT_EN);
break;
case GPIO_VGA_DDC:
if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
/* FIXME: Maybe add a property to select VGA or DVI port? */
}
break;
case GPIO_DVI_DDC:
if (s->dev_id != PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.gpio_dvi_ddc = ati_i2c(&s->bbi2c, data, 0);
}
break;
case GPIO_MONID ... GPIO_MONID + 3:
/* FIXME What does Radeon have here? */
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
ati_reg_write_offs(&s->regs.gpio_monid,
addr - GPIO_MONID, data, size);
/*
* Rage128p accesses DDC used to get EDID via these bits.
* Because some drivers access this via multiple byte writes
* we have to be careful when we send bits to avoid spurious
* changes in bitbang_i2c state. So only do it when mask is set
* and either the enable bits are changed or output bits changed
* while enabled.
*/
if ((s->regs.gpio_monid & BIT(25)) &&
((addr <= GPIO_MONID + 2 && addr + size > GPIO_MONID + 2) ||
(addr == GPIO_MONID && (s->regs.gpio_monid & 0x60000)))) {
s->regs.gpio_monid = ati_i2c(&s->bbi2c, s->regs.gpio_monid, 1);
}
}
break;
case PALETTE_INDEX ... PALETTE_INDEX + 3:
if (size == 4) {
vga_ioport_write(&s->vga, VGA_PEL_IR, (data >> 16) & 0xff);
vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
} else {
if (addr == PALETTE_INDEX) {
vga_ioport_write(&s->vga, VGA_PEL_IW, data & 0xff);
} else {
vga_ioport_write(&s->vga, VGA_PEL_IR, data & 0xff);
}
}
break;
case PALETTE_DATA ... PALETTE_DATA + 3:
data <<= addr - PALETTE_DATA;
data = bswap32(data) >> 8;
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
data >>= 8;
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
data >>= 8;
vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff);
break;
case CNFG_CNTL:
s->regs.config_cntl = data;
break;
case CRTC_H_TOTAL_DISP:
s->regs.crtc_h_total_disp = data & 0x07ff07ff;
break;
case CRTC_H_SYNC_STRT_WID:
s->regs.crtc_h_sync_strt_wid = data & 0x17bf1fff;
break;
case CRTC_V_TOTAL_DISP:
s->regs.crtc_v_total_disp = data & 0x0fff0fff;
break;
case CRTC_V_SYNC_STRT_WID:
s->regs.crtc_v_sync_strt_wid = data & 0x9f0fff;
break;
case CRTC_OFFSET:
s->regs.crtc_offset = data & 0xc7ffffff;
break;
case CRTC_OFFSET_CNTL:
s->regs.crtc_offset_cntl = data; /* FIXME */
break;
case CRTC_PITCH:
s->regs.crtc_pitch = data & 0x07ff07ff;
break;
case 0xf00 ... 0xfff:
/* read-only copy of PCI config space so ignore writes */
break;
case CUR_OFFSET ... CUR_OFFSET + 3:
{
uint32_t t = s->regs.cur_offset;
ati_reg_write_offs(&t, addr - CUR_OFFSET, data, size);
t &= 0x87fffff0;
if (s->regs.cur_offset != t) {
s->regs.cur_offset = t;
ati_cursor_define(s);
}
break;
}
case CUR_HORZ_VERT_POSN ... CUR_HORZ_VERT_POSN + 3:
{
uint32_t t = s->regs.cur_hv_pos | (s->regs.cur_offset & BIT(31));
ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_POSN, data, size);
s->regs.cur_hv_pos = t & 0x3fff0fff;
if (t & BIT(31)) {
s->regs.cur_offset |= t & BIT(31);
} else if (s->regs.cur_offset & BIT(31)) {
s->regs.cur_offset &= ~BIT(31);
ati_cursor_define(s);
}
if (!s->cursor_guest_mode &&
(s->regs.crtc_gen_cntl & CRTC2_CUR_EN) && !(t & BIT(31))) {
dpy_mouse_set(s->vga.con, s->regs.cur_hv_pos >> 16,
s->regs.cur_hv_pos & 0xffff, 1);
}
break;
}
case CUR_HORZ_VERT_OFF:
{
uint32_t t = s->regs.cur_hv_offs | (s->regs.cur_offset & BIT(31));
ati_reg_write_offs(&t, addr - CUR_HORZ_VERT_OFF, data, size);
s->regs.cur_hv_offs = t & 0x3f003f;
if (t & BIT(31)) {
s->regs.cur_offset |= t & BIT(31);
} else if (s->regs.cur_offset & BIT(31)) {
s->regs.cur_offset &= ~BIT(31);
ati_cursor_define(s);
}
break;
}
case CUR_CLR0 ... CUR_CLR0 + 3:
{
uint32_t t = s->regs.cur_color0;
ati_reg_write_offs(&t, addr - CUR_CLR0, data, size);
t &= 0xffffff;
if (s->regs.cur_color0 != t) {
s->regs.cur_color0 = t;
ati_cursor_define(s);
}
break;
}
case CUR_CLR1 ... CUR_CLR1 + 3:
/*
* Update cursor unconditionally here because some clients set up
* other registers before actually writing cursor data to memory at
* offset so we would miss cursor change unless always updating here
*/
ati_reg_write_offs(&s->regs.cur_color1, addr - CUR_CLR1, data, size);
s->regs.cur_color1 &= 0xffffff;
ati_cursor_define(s);
break;
case DST_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_offset = data & 0xfffffff0;
} else {
s->regs.dst_offset = data & 0xfffffc00;
}
break;
case DST_PITCH:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_pitch = data & 0x3fff;
s->regs.dst_tile = (data >> 16) & 1;
} else {
s->regs.dst_pitch = data & 0x3ff0;
}
break;
case DST_TILE:
if (s->dev_id == PCI_DEVICE_ID_ATI_RADEON_QY) {
s->regs.dst_tile = data & 3;
}
break;
case DST_WIDTH:
s->regs.dst_width = data & 0x3fff;
ati_2d_blt(s);
break;
case DST_HEIGHT:
s->regs.dst_height = data & 0x3fff;
break;
case SRC_X:
s->regs.src_x = data & 0x3fff;
break;
case SRC_Y:
s->regs.src_y = data & 0x3fff;
break;
case DST_X:
s->regs.dst_x = data & 0x3fff;
break;
case DST_Y:
s->regs.dst_y = data & 0x3fff;
break;
case SRC_PITCH_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_offset = (data & 0x1fffff) << 5;
s->regs.src_pitch = (data & 0x7fe00000) >> 21;
s->regs.src_tile = data >> 31;
} else {
s->regs.src_offset = (data & 0x3fffff) << 10;
s->regs.src_pitch = (data & 0x3fc00000) >> 16;
s->regs.src_tile = (data >> 30) & 1;
}
break;
case DST_PITCH_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.dst_offset = (data & 0x1fffff) << 5;
s->regs.dst_pitch = (data & 0x7fe00000) >> 21;
s->regs.dst_tile = data >> 31;
} else {
s->regs.dst_offset = (data & 0x3fffff) << 10;
s->regs.dst_pitch = (data & 0x3fc00000) >> 16;
s->regs.dst_tile = data >> 30;
}
break;
case SRC_Y_X:
s->regs.src_x = data & 0x3fff;
s->regs.src_y = (data >> 16) & 0x3fff;
break;
case DST_Y_X:
s->regs.dst_x = data & 0x3fff;
s->regs.dst_y = (data >> 16) & 0x3fff;
break;
case DST_HEIGHT_WIDTH:
s->regs.dst_width = data & 0x3fff;
s->regs.dst_height = (data >> 16) & 0x3fff;
ati_2d_blt(s);
break;
case DP_GUI_MASTER_CNTL:
s->regs.dp_gui_master_cntl = data & 0xf800000f;
s->regs.dp_datatype = (data & 0x0f00) >> 8 | (data & 0x30f0) << 4 |
(data & 0x4000) << 16;
s->regs.dp_mix = (data & GMC_ROP3_MASK) | (data & 0x7000000) >> 16;
break;
case DST_WIDTH_X:
s->regs.dst_x = data & 0x3fff;
s->regs.dst_width = (data >> 16) & 0x3fff;
ati_2d_blt(s);
break;
case SRC_X_Y:
s->regs.src_y = data & 0x3fff;
s->regs.src_x = (data >> 16) & 0x3fff;
break;
case DST_X_Y:
s->regs.dst_y = data & 0x3fff;
s->regs.dst_x = (data >> 16) & 0x3fff;
break;
case DST_WIDTH_HEIGHT:
s->regs.dst_height = data & 0x3fff;
s->regs.dst_width = (data >> 16) & 0x3fff;
ati_2d_blt(s);
break;
case DST_HEIGHT_Y:
s->regs.dst_y = data & 0x3fff;
s->regs.dst_height = (data >> 16) & 0x3fff;
break;
case SRC_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_offset = data & 0xfffffff0;
} else {
s->regs.src_offset = data & 0xfffffc00;
}
break;
case SRC_PITCH:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.src_pitch = data & 0x3fff;
s->regs.src_tile = (data >> 16) & 1;
} else {
s->regs.src_pitch = data & 0x3ff0;
}
break;
case DP_BRUSH_BKGD_CLR:
s->regs.dp_brush_bkgd_clr = data;
break;
case DP_BRUSH_FRGD_CLR:
s->regs.dp_brush_frgd_clr = data;
break;
case DP_CNTL:
s->regs.dp_cntl = data;
break;
case DP_DATATYPE:
s->regs.dp_datatype = data & 0xe0070f0f;
break;
case DP_MIX:
s->regs.dp_mix = data & 0x00ff0700;
break;
case DP_WRITE_MASK:
s->regs.dp_write_mask = data;
break;
case DEFAULT_OFFSET:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.default_offset = data & 0xfffffff0;
} else {
/* Radeon has DEFAULT_PITCH_OFFSET here like DST_PITCH_OFFSET */
s->regs.default_offset = (data & 0x3fffff) << 10;
s->regs.default_pitch = (data & 0x3fc00000) >> 16;
s->regs.default_tile = data >> 30;
}
break;
case DEFAULT_PITCH:
if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
s->regs.default_pitch = data & 0x3fff;
s->regs.default_tile = (data >> 16) & 1;
}
break;
case DEFAULT_SC_BOTTOM_RIGHT:
s->regs.default_sc_bottom_right = data & 0x3fff3fff;
break;
default:
break;
}
}