in hw/arm/armsse.c [901:1645]
static void armsse_realize(DeviceState *dev, Error **errp)
{
ARMSSE *s = ARM_SSE(dev);
ARMSSEClass *asc = ARM_SSE_GET_CLASS(dev);
const ARMSSEInfo *info = asc->info;
const ARMSSEDeviceInfo *devinfo;
int i;
MemoryRegion *mr;
SysBusDevice *sbd_apb_ppc0;
SysBusDevice *sbd_secctl;
DeviceState *dev_apb_ppc0;
DeviceState *dev_apb_ppc1;
DeviceState *dev_secctl;
DeviceState *dev_splitter;
uint32_t addr_width_max;
ERRP_GUARD();
if (!s->board_memory) {
error_setg(errp, "memory property was not set");
return;
}
if (!clock_has_source(s->mainclk)) {
error_setg(errp, "MAINCLK clock was not connected");
}
if (!clock_has_source(s->s32kclk)) {
error_setg(errp, "S32KCLK clock was not connected");
}
assert(info->num_cpus <= SSE_MAX_CPUS);
/* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
assert(is_power_of_2(info->sram_banks));
addr_width_max = 24 - ctz32(info->sram_banks);
if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) {
error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d",
addr_width_max);
return;
}
/* Handling of which devices should be available only to secure
* code is usually done differently for M profile than for A profile.
* Instead of putting some devices only into the secure address space,
* devices exist in both address spaces but with hard-wired security
* permissions that will cause the CPU to fault for non-secure accesses.
*
* The ARMSSE has an IDAU (Implementation Defined Access Unit),
* which specifies hard-wired security permissions for different
* areas of the physical address space. For the ARMSSE IDAU, the
* top 4 bits of the physical address are the IDAU region ID, and
* if bit 28 (ie the lowest bit of the ID) is 0 then this is an NS
* region, otherwise it is an S region.
*
* The various devices and RAMs are generally all mapped twice,
* once into a region that the IDAU defines as secure and once
* into a non-secure region. They sit behind either a Memory
* Protection Controller (for RAM) or a Peripheral Protection
* Controller (for devices), which allow a more fine grained
* configuration of whether non-secure accesses are permitted.
*
* (The other place that guest software can configure security
* permissions is in the architected SAU (Security Attribution
* Unit), which is entirely inside the CPU. The IDAU can upgrade
* the security attributes for a region to more restrictive than
* the SAU specifies, but cannot downgrade them.)
*
* 0x10000000..0x1fffffff alias of 0x00000000..0x0fffffff
* 0x20000000..0x2007ffff 32KB FPGA block RAM
* 0x30000000..0x3fffffff alias of 0x20000000..0x2fffffff
* 0x40000000..0x4000ffff base peripheral region 1
* 0x40010000..0x4001ffff CPU peripherals (none for ARMSSE)
* 0x40020000..0x4002ffff system control element peripherals
* 0x40080000..0x400fffff base peripheral region 2
* 0x50000000..0x5fffffff alias of 0x40000000..0x4fffffff
*/
memory_region_add_subregion_overlap(&s->container, 0, s->board_memory, -2);
for (i = 0; i < info->num_cpus; i++) {
DeviceState *cpudev = DEVICE(&s->armv7m[i]);
Object *cpuobj = OBJECT(&s->armv7m[i]);
int j;
char *gpioname;
qdev_connect_clock_in(cpudev, "cpuclk", s->mainclk);
/* The SSE subsystems do not wire up a systick refclk */
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + NUM_SSE_IRQS);
/*
* In real hardware the initial Secure VTOR is set from the INITSVTOR*
* registers in the IoT Kit System Control Register block. In QEMU
* we set the initial value here, and also the reset value of the
* sysctl register, from this object's QOM init-svtor property.
* If the guest changes the INITSVTOR* registers at runtime then the
* code in iotkit-sysctl.c will update the CPU init-svtor property
* (which will then take effect on the next CPU warm-reset).
*
* Note that typically a board using the SSE-200 will have a system
* control processor whose boot firmware initializes the INITSVTOR*
* registers before powering up the CPUs. QEMU doesn't emulate
* the control processor, so instead we behave in the way that the
* firmware does: the initial value should be set by the board code
* (using the init-svtor property on the ARMSSE object) to match
* whatever its firmware does.
*/
qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
/*
* CPUs start powered down if the corresponding bit in the CPUWAIT
* register is 1. In real hardware the CPUWAIT register reset value is
* a configurable property of the SSE-200 (via the CPUWAIT0_RST and
* CPUWAIT1_RST parameters), but since all the boards we care about
* start CPU0 and leave CPU1 powered off, we hard-code that in
* info->cpuwait_rst for now. We can add QOM properties for this
* later if necessary.
*/
if (extract32(info->cpuwait_rst, i, 1)) {
if (!object_property_set_bool(cpuobj, "start-powered-off", true,
errp)) {
return;
}
}
if (!s->cpu_fpu[i]) {
if (!object_property_set_bool(cpuobj, "vfp", false, errp)) {
return;
}
}
if (!s->cpu_dsp[i]) {
if (!object_property_set_bool(cpuobj, "dsp", false, errp)) {
return;
}
}
if (i > 0) {
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
&s->container_alias[i - 1], -1);
} else {
memory_region_add_subregion_overlap(&s->cpu_container[i], 0,
&s->container, -1);
}
object_property_set_link(cpuobj, "memory",
OBJECT(&s->cpu_container[i]), &error_abort);
object_property_set_link(cpuobj, "idau", OBJECT(s), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(cpuobj), errp)) {
return;
}
/*
* The cluster must be realized after the armv7m container, as
* the container's CPU object is only created on realize, and the
* CPU must exist and have been parented into the cluster before
* the cluster is realized.
*/
if (!qdev_realize(DEVICE(&s->cluster[i]), NULL, errp)) {
return;
}
/* Connect EXP_IRQ/EXP_CPUn_IRQ GPIOs to the NVIC's lines 32 and up */
s->exp_irqs[i] = g_new(qemu_irq, s->exp_numirq);
for (j = 0; j < s->exp_numirq; j++) {
s->exp_irqs[i][j] = qdev_get_gpio_in(cpudev, j + NUM_SSE_IRQS);
}
if (i == 0) {
gpioname = g_strdup("EXP_IRQ");
} else {
gpioname = g_strdup_printf("EXP_CPU%d_IRQ", i);
}
qdev_init_gpio_in_named_with_opaque(dev, armsse_exp_irq,
s->exp_irqs[i],
gpioname, s->exp_numirq);
g_free(gpioname);
}
/* Wire up the splitters that connect common IRQs to all CPUs */
if (info->num_cpus > 1) {
for (i = 0; i < ARRAY_SIZE(s->cpu_irq_splitter); i++) {
if (info->irq_is_common[i]) {
Object *splitter = OBJECT(&s->cpu_irq_splitter[i]);
DeviceState *devs = DEVICE(splitter);
int cpunum;
if (!object_property_set_int(splitter, "num-lines",
info->num_cpus, errp)) {
return;
}
if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
return;
}
for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
qdev_connect_gpio_out(devs, cpunum,
qdev_get_gpio_in(cpudev, i));
}
}
}
}
/* Set up the big aliases first */
make_alias(s, &s->alias1, &s->container, "alias 1",
0x10000000, 0x10000000, 0x00000000);
make_alias(s, &s->alias2, &s->container,
"alias 2", 0x30000000, 0x10000000, 0x20000000);
/* The 0x50000000..0x5fffffff region is not a pure alias: it has
* a few extra devices that only appear there (generally the
* control interfaces for the protection controllers).
* We implement this by mapping those devices over the top of this
* alias MR at a higher priority. Some of the devices in this range
* are per-CPU, so we must put this alias in the per-cpu containers.
*/
for (i = 0; i < info->num_cpus; i++) {
make_alias(s, &s->alias3[i], &s->cpu_container[i],
"alias 3", 0x50000000, 0x10000000, 0x40000000);
}
/* Security controller */
object_property_set_int(OBJECT(&s->secctl), "sse-version",
info->sse_version, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->secctl), errp)) {
return;
}
sbd_secctl = SYS_BUS_DEVICE(&s->secctl);
dev_secctl = DEVICE(&s->secctl);
sysbus_mmio_map(sbd_secctl, 0, 0x50080000);
sysbus_mmio_map(sbd_secctl, 1, 0x40080000);
s->nsc_cfg_in = qemu_allocate_irq(nsccfg_handler, s, 1);
qdev_connect_gpio_out_named(dev_secctl, "nsc_cfg", 0, s->nsc_cfg_in);
/* The sec_resp_cfg output from the security controller must be split into
* multiple lines, one for each of the PPCs within the ARMSSE and one
* that will be an output from the ARMSSE to the system.
*/
if (!object_property_set_int(OBJECT(&s->sec_resp_splitter),
"num-lines", 3, errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->sec_resp_splitter), NULL, errp)) {
return;
}
dev_splitter = DEVICE(&s->sec_resp_splitter);
qdev_connect_gpio_out_named(dev_secctl, "sec_resp_cfg", 0,
qdev_get_gpio_in(dev_splitter, 0));
/* Each SRAM bank lives behind its own Memory Protection Controller */
for (i = 0; i < info->sram_banks; i++) {
char *ramname = g_strdup_printf("armsse.sram%d", i);
SysBusDevice *sbd_mpc;
uint32_t sram_bank_size = 1 << s->sram_addr_width;
memory_region_init_ram(&s->sram[i], NULL, ramname,
sram_bank_size, errp);
g_free(ramname);
if (*errp) {
return;
}
object_property_set_link(OBJECT(&s->mpc[i]), "downstream",
OBJECT(&s->sram[i]), &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->mpc[i]), errp)) {
return;
}
/* Map the upstream end of the MPC into the right place... */
sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
memory_region_add_subregion(&s->container,
info->sram_bank_base + i * sram_bank_size,
sysbus_mmio_get_region(sbd_mpc, 1));
/* ...and its register interface */
memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
sysbus_mmio_get_region(sbd_mpc, 0));
}
/* We must OR together lines from the MPC splitters to go to the NVIC */
if (!object_property_set_int(OBJECT(&s->mpc_irq_orgate), "num-lines",
IOTS_NUM_EXP_MPC + info->sram_banks,
errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->mpc_irq_orgate), NULL, errp)) {
return;
}
qdev_connect_gpio_out(DEVICE(&s->mpc_irq_orgate), 0,
armsse_get_common_irq_in(s, 9));
/* This OR gate wires together outputs from the secure watchdogs to NMI */
if (!object_property_set_int(OBJECT(&s->nmi_orgate), "num-lines", 2,
errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->nmi_orgate), NULL, errp)) {
return;
}
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI", 0));
/* The SSE-300 has a System Counter / System Timestamp Generator */
if (info->has_sse_counter) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter);
qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk);
if (!sysbus_realize(sbd, errp)) {
return;
}
/*
* The control frame is only in the Secure region;
* the status frame is in the NS region (and visible in the
* S region via the alias mapping).
*/
memory_region_add_subregion(&s->container, 0x58100000,
sysbus_mmio_get_region(sbd, 0));
memory_region_add_subregion(&s->container, 0x48101000,
sysbus_mmio_get_region(sbd, 1));
}
if (info->has_tcms) {
/* The SSE-300 has an ITCM at 0x0000_0000 and a DTCM at 0x2000_0000 */
memory_region_init_ram(&s->itcm, NULL, "sse300-itcm", 512 * KiB, errp);
if (*errp) {
return;
}
memory_region_init_ram(&s->dtcm, NULL, "sse300-dtcm", 512 * KiB, errp);
if (*errp) {
return;
}
memory_region_add_subregion(&s->container, 0x00000000, &s->itcm);
memory_region_add_subregion(&s->container, 0x20000000, &s->dtcm);
}
/* Devices behind APB PPC0:
* 0x40000000: timer0
* 0x40001000: timer1
* 0x40002000: dual timer
* 0x40003000: MHU0 (SSE-200 only)
* 0x40004000: MHU1 (SSE-200 only)
* We must configure and realize each downstream device and connect
* it to the appropriate PPC port; then we can realize the PPC and
* map its upstream ends to the right place in the container.
*/
for (devinfo = info->devinfo; devinfo->name; devinfo++) {
SysBusDevice *sbd;
qemu_irq irq;
if (!strcmp(devinfo->type, TYPE_CMSDK_APB_TIMER)) {
sbd = SYS_BUS_DEVICE(&s->timer[devinfo->index]);
qdev_connect_clock_in(DEVICE(sbd), "pclk",
devinfo->slowclk ? s->s32kclk : s->mainclk);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_DUALTIMER)) {
sbd = SYS_BUS_DEVICE(&s->dualtimer);
qdev_connect_clock_in(DEVICE(sbd), "TIMCLK", s->mainclk);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_SSE_TIMER)) {
sbd = SYS_BUS_DEVICE(&s->sse_timer[devinfo->index]);
assert(info->has_sse_counter);
object_property_set_link(OBJECT(sbd), "counter",
OBJECT(&s->sse_counter), &error_abort);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_CMSDK_APB_WATCHDOG)) {
sbd = SYS_BUS_DEVICE(&s->cmsdk_watchdog[devinfo->index]);
qdev_connect_clock_in(DEVICE(sbd), "WDOGCLK",
devinfo->slowclk ? s->s32kclk : s->mainclk);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSINFO)) {
sbd = SYS_BUS_DEVICE(&s->sysinfo);
object_property_set_int(OBJECT(&s->sysinfo), "SYS_VERSION",
info->sys_version, &error_abort);
object_property_set_int(OBJECT(&s->sysinfo), "SYS_CONFIG",
armsse_sys_config_value(s, info),
&error_abort);
object_property_set_int(OBJECT(&s->sysinfo), "sse-version",
info->sse_version, &error_abort);
object_property_set_int(OBJECT(&s->sysinfo), "IIDR",
info->iidr, &error_abort);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_IOTKIT_SYSCTL)) {
/* System control registers */
sbd = SYS_BUS_DEVICE(&s->sysctl);
object_property_set_int(OBJECT(&s->sysctl), "sse-version",
info->sse_version, &error_abort);
object_property_set_int(OBJECT(&s->sysctl), "CPUWAIT_RST",
info->cpuwait_rst, &error_abort);
object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR0_RST",
s->init_svtor, &error_abort);
object_property_set_int(OBJECT(&s->sysctl), "INITSVTOR1_RST",
s->init_svtor, &error_abort);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else if (!strcmp(devinfo->type, TYPE_UNIMPLEMENTED_DEVICE)) {
sbd = SYS_BUS_DEVICE(&s->unimp[devinfo->index]);
qdev_prop_set_string(DEVICE(sbd), "name", devinfo->name);
qdev_prop_set_uint64(DEVICE(sbd), "size", devinfo->size);
if (!sysbus_realize(sbd, errp)) {
return;
}
mr = sysbus_mmio_get_region(sbd, 0);
} else {
g_assert_not_reached();
}
switch (devinfo->irq) {
case NO_IRQ:
irq = NULL;
break;
case 0 ... NUM_SSE_IRQS - 1:
irq = armsse_get_common_irq_in(s, devinfo->irq);
break;
case NMI_0:
case NMI_1:
irq = qdev_get_gpio_in(DEVICE(&s->nmi_orgate),
devinfo->irq - NMI_0);
break;
default:
g_assert_not_reached();
}
if (irq) {
sysbus_connect_irq(sbd, 0, irq);
}
/*
* Devices connected to a PPC are connected to the port here;
* we will map the upstream end of that port to the right address
* in the container later after the PPC has been realized.
* Devices not connected to a PPC can be mapped immediately.
*/
if (devinfo->ppc != NO_PPC) {
TZPPC *ppc = &s->apb_ppc[devinfo->ppc];
g_autofree char *portname = g_strdup_printf("port[%d]",
devinfo->ppc_port);
object_property_set_link(OBJECT(ppc), portname, OBJECT(mr),
&error_abort);
} else {
memory_region_add_subregion(&s->container, devinfo->addr, mr);
}
}
if (info->has_mhus) {
/*
* An SSE-200 with only one CPU should have only one MHU created,
* with the region where the second MHU usually is being RAZ/WI.
* We don't implement that SSE-200 config; if we want to support
* it then this code needs to be enhanced to handle creating the
* RAZ/WI region instead of the second MHU.
*/
assert(info->num_cpus == ARRAY_SIZE(s->mhu));
for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
char *port;
int cpunum;
SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->mhu[i]), errp)) {
return;
}
port = g_strdup_printf("port[%d]", i + 3);
mr = sysbus_mmio_get_region(mhu_sbd, 0);
object_property_set_link(OBJECT(&s->apb_ppc[0]), port, OBJECT(mr),
&error_abort);
g_free(port);
/*
* Each MHU has an irq line for each CPU:
* MHU 0 irq line 0 -> CPU 0 IRQ 6
* MHU 0 irq line 1 -> CPU 1 IRQ 6
* MHU 1 irq line 0 -> CPU 0 IRQ 7
* MHU 1 irq line 1 -> CPU 1 IRQ 7
*/
for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
sysbus_connect_irq(mhu_sbd, cpunum,
qdev_get_gpio_in(cpudev, 6 + i));
}
}
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[0]), errp)) {
return;
}
sbd_apb_ppc0 = SYS_BUS_DEVICE(&s->apb_ppc[0]);
dev_apb_ppc0 = DEVICE(&s->apb_ppc[0]);
if (info->has_mhus) {
mr = sysbus_mmio_get_region(sbd_apb_ppc0, 3);
memory_region_add_subregion(&s->container, 0x40003000, mr);
mr = sysbus_mmio_get_region(sbd_apb_ppc0, 4);
memory_region_add_subregion(&s->container, 0x40004000, mr);
}
for (i = 0; i < IOTS_APB_PPC0_NUM_PORTS; i++) {
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_nonsec", i,
qdev_get_gpio_in_named(dev_apb_ppc0,
"cfg_nonsec", i));
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_ap", i,
qdev_get_gpio_in_named(dev_apb_ppc0,
"cfg_ap", i));
}
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_enable", 0,
qdev_get_gpio_in_named(dev_apb_ppc0,
"irq_enable", 0));
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc0_irq_clear", 0,
qdev_get_gpio_in_named(dev_apb_ppc0,
"irq_clear", 0));
qdev_connect_gpio_out(dev_splitter, 0,
qdev_get_gpio_in_named(dev_apb_ppc0,
"cfg_sec_resp", 0));
/* All the PPC irq lines (from the 2 internal PPCs and the 8 external
* ones) are sent individually to the security controller, and also
* ORed together to give a single combined PPC interrupt to the NVIC.
*/
if (!object_property_set_int(OBJECT(&s->ppc_irq_orgate),
"num-lines", NUM_PPCS, errp)) {
return;
}
if (!qdev_realize(DEVICE(&s->ppc_irq_orgate), NULL, errp)) {
return;
}
qdev_connect_gpio_out(DEVICE(&s->ppc_irq_orgate), 0,
armsse_get_common_irq_in(s, 10));
/*
* 0x40010000 .. 0x4001ffff (and the 0x5001000... secure-only alias):
* private per-CPU region (all these devices are SSE-200 only):
* 0x50010000: L1 icache control registers
* 0x50011000: CPUSECCTRL (CPU local security control registers)
* 0x4001f000 and 0x5001f000: CPU_IDENTITY register block
* The SSE-300 has an extra:
* 0x40012000 and 0x50012000: CPU_PWRCTRL register block
*/
if (info->has_cachectrl) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("cachectrl%d", i);
MemoryRegion *mr;
qdev_prop_set_string(DEVICE(&s->cachectrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cachectrl[i]), "size", 0x1000);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cachectrl[i]), errp)) {
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cachectrl[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x50010000, mr);
}
}
if (info->has_cpusecctrl) {
for (i = 0; i < info->num_cpus; i++) {
char *name = g_strdup_printf("CPUSECCTRL%d", i);
MemoryRegion *mr;
qdev_prop_set_string(DEVICE(&s->cpusecctrl[i]), "name", name);
g_free(name);
qdev_prop_set_uint64(DEVICE(&s->cpusecctrl[i]), "size", 0x1000);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpusecctrl[i]), errp)) {
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpusecctrl[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x50011000, mr);
}
}
if (info->has_cpuid) {
for (i = 0; i < info->num_cpus; i++) {
MemoryRegion *mr;
qdev_prop_set_uint32(DEVICE(&s->cpuid[i]), "CPUID", i);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpuid[i]), errp)) {
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpuid[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x4001F000, mr);
}
}
if (info->has_cpu_pwrctrl) {
for (i = 0; i < info->num_cpus; i++) {
MemoryRegion *mr;
if (!sysbus_realize(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), errp)) {
return;
}
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpu_pwrctrl[i]), 0);
memory_region_add_subregion(&s->cpu_container[i], 0x40012000, mr);
}
}
if (!sysbus_realize(SYS_BUS_DEVICE(&s->apb_ppc[1]), errp)) {
return;
}
dev_apb_ppc1 = DEVICE(&s->apb_ppc[1]);
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_nonsec", 0,
qdev_get_gpio_in_named(dev_apb_ppc1,
"cfg_nonsec", 0));
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_ap", 0,
qdev_get_gpio_in_named(dev_apb_ppc1,
"cfg_ap", 0));
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_enable", 0,
qdev_get_gpio_in_named(dev_apb_ppc1,
"irq_enable", 0));
qdev_connect_gpio_out_named(dev_secctl, "apb_ppc1_irq_clear", 0,
qdev_get_gpio_in_named(dev_apb_ppc1,
"irq_clear", 0));
qdev_connect_gpio_out(dev_splitter, 1,
qdev_get_gpio_in_named(dev_apb_ppc1,
"cfg_sec_resp", 0));
/*
* Now both PPCs are realized we can map the upstream ends of
* ports which correspond to entries in the devinfo array.
* The ports which are connected to non-devinfo devices have
* already been mapped.
*/
for (devinfo = info->devinfo; devinfo->name; devinfo++) {
SysBusDevice *ppc_sbd;
if (devinfo->ppc == NO_PPC) {
continue;
}
ppc_sbd = SYS_BUS_DEVICE(&s->apb_ppc[devinfo->ppc]);
mr = sysbus_mmio_get_region(ppc_sbd, devinfo->ppc_port);
memory_region_add_subregion(&s->container, devinfo->addr, mr);
}
for (i = 0; i < ARRAY_SIZE(s->ppc_irq_splitter); i++) {
Object *splitter = OBJECT(&s->ppc_irq_splitter[i]);
if (!object_property_set_int(splitter, "num-lines", 2, errp)) {
return;
}
if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
return;
}
}
for (i = 0; i < IOTS_NUM_AHB_EXP_PPC; i++) {
char *ppcname = g_strdup_printf("ahb_ppcexp%d", i);
armsse_forward_ppc(s, ppcname, i);
g_free(ppcname);
}
for (i = 0; i < IOTS_NUM_APB_EXP_PPC; i++) {
char *ppcname = g_strdup_printf("apb_ppcexp%d", i);
armsse_forward_ppc(s, ppcname, i + IOTS_NUM_AHB_EXP_PPC);
g_free(ppcname);
}
for (i = NUM_EXTERNAL_PPCS; i < NUM_PPCS; i++) {
/* Wire up IRQ splitter for internal PPCs */
DeviceState *devs = DEVICE(&s->ppc_irq_splitter[i]);
char *gpioname = g_strdup_printf("apb_ppc%d_irq_status",
i - NUM_EXTERNAL_PPCS);
TZPPC *ppc = &s->apb_ppc[i - NUM_EXTERNAL_PPCS];
qdev_connect_gpio_out(devs, 0,
qdev_get_gpio_in_named(dev_secctl, gpioname, 0));
qdev_connect_gpio_out(devs, 1,
qdev_get_gpio_in(DEVICE(&s->ppc_irq_orgate), i));
qdev_connect_gpio_out_named(DEVICE(ppc), "irq", 0,
qdev_get_gpio_in(devs, 0));
g_free(gpioname);
}
/* Wire up the splitters for the MPC IRQs */
for (i = 0; i < IOTS_NUM_EXP_MPC + info->sram_banks; i++) {
SplitIRQ *splitter = &s->mpc_irq_splitter[i];
DeviceState *dev_splitter = DEVICE(splitter);
if (!object_property_set_int(OBJECT(splitter), "num-lines", 2,
errp)) {
return;
}
if (!qdev_realize(DEVICE(splitter), NULL, errp)) {
return;
}
if (i < IOTS_NUM_EXP_MPC) {
/* Splitter input is from GPIO input line */
s->mpcexp_status_in[i] = qdev_get_gpio_in(dev_splitter, 0);
qdev_connect_gpio_out(dev_splitter, 0,
qdev_get_gpio_in_named(dev_secctl,
"mpcexp_status", i));
} else {
/* Splitter input is from our own MPC */
qdev_connect_gpio_out_named(DEVICE(&s->mpc[i - IOTS_NUM_EXP_MPC]),
"irq", 0,
qdev_get_gpio_in(dev_splitter, 0));
qdev_connect_gpio_out(dev_splitter, 0,
qdev_get_gpio_in_named(dev_secctl,
"mpc_status",
i - IOTS_NUM_EXP_MPC));
}
qdev_connect_gpio_out(dev_splitter, 1,
qdev_get_gpio_in(DEVICE(&s->mpc_irq_orgate), i));
}
/* Create GPIO inputs which will pass the line state for our
* mpcexp_irq inputs to the correct splitter devices.
*/
qdev_init_gpio_in_named(dev, armsse_mpcexp_status, "mpcexp_status",
IOTS_NUM_EXP_MPC);
armsse_forward_sec_resp_cfg(s);
/* Forward the MSC related signals */
qdev_pass_gpios(dev_secctl, dev, "mscexp_status");
qdev_pass_gpios(dev_secctl, dev, "mscexp_clear");
qdev_pass_gpios(dev_secctl, dev, "mscexp_ns");
qdev_connect_gpio_out_named(dev_secctl, "msc_irq", 0,
armsse_get_common_irq_in(s, 11));
/*
* Expose our container region to the board model; this corresponds
* to the AHB Slave Expansion ports which allow bus master devices
* (eg DMA controllers) in the board model to make transactions into
* devices in the ARMSSE.
*/
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->container);
}