in drivers/ram/mediatek/ddr3-mt7629.c [268:680]
static int mtk_ddr3_init(struct udevice *dev)
{
struct mtk_ddr3_priv *priv = dev_get_priv(dev);
int ret;
ret = clk_set_parent(&priv->phy, &priv->phy_mux);
if (ret)
return ret;
/* EMI Setting */
writel(0x00003010, priv->emi + EMI_CONA);
writel(0x00000000, priv->emi + EMI_CONF);
writel(0x000006b8, priv->emi + EMI_CONM);
/* DQS */
writel(0x20c00, priv->dramc_ao + DRAMC_SHU1_DRVING1);
/* Clock */
writel(0x8320c83, priv->dramc_ao + DRAMC_SHU1_DRVING2);
/* DDRPHY setting */
writel(0x2201, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
writel(0xe08, priv->ddrphy + DDRPHY_CA_CMD5);
writel(0x60e, priv->ddrphy + DDRPHY_SHU1_CA_CMD5);
writel(0x0, priv->ddrphy + DDRPHY_MISC_SPM_CTRL1);
writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL0);
writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_SPM_CTRL2);
writel(0x6003bf, priv->ddrphy + DDRPHY_MISC_CG_CTRL2);
writel(0x13300000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
writel(0x1, priv->ddrphy + DDRPHY_SHU1_CA_CMD7);
writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
writel(0xfff0, priv->ddrphy + DDRPHY_CA_CMD2);
writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
writel(0x0, priv->ddrphy + DDRPHY_B1_DQ2);
writel(0x7, priv->ddrphy + DDRPHY_MISC_RXDVS1);
writel(0x10, priv->ddrphy + DDRPHY_PLL3);
writel(0x8e8e0000, priv->ddrphy + DDRPHY_MISC_VREF_CTRL);
writel(0x2e0040, priv->ddrphy + DDRPHY_MISC_IMP_CTRL0);
writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
writel(0x50060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
udelay(1);
writel(0x10, priv->ddrphy + DDRPHY_B0_DQ3);
writel(0x10, priv->ddrphy + DDRPHY_B1_DQ3);
writel(0x3f600, priv->ddrphy + DDRPHY_MISC_CG_CTRL1);
writel(0x1010, priv->ddrphy + DDRPHY_B0_DQ4);
writel(0x1110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
writel(0x10c10d0, priv->ddrphy + DDRPHY_B0_DQ6);
writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
writel(0x1010, priv->ddrphy + DDRPHY_B1_DQ4);
writel(0x1110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
writel(0x10c10d0, priv->ddrphy + DDRPHY_B1_DQ6);
writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
writel(0x7fffffc, priv->ddrphy + DDRPHY_CA_CMD3);
writel(0xc0010, priv->ddrphy + DDRPHY_CA_CMD6);
writel(0x101, priv->ddrphy + DDRPHY_SHU1_CA_CMD2);
writel(0x41e, priv->ddrphy + DDRPHY_B0_DQ3);
writel(0x41e, priv->ddrphy + DDRPHY_B1_DQ3);
writel(0x180101, priv->ddrphy + DDRPHY_CA_CMD8);
writel(0x0, priv->ddrphy + DDRPHY_MISC_IMP_CTRL1);
writel(0x11400000, priv->ddrphy + DDRPHY_MISC_CG_CTRL4);
writel(0xfff0f0f0, priv->ddrphy + DDRPHY_MISC_SHU_OPT);
writel(0x1f, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
writel(0x40000, priv->ddrphy + DDRPHY_PLL4);
writel(0x0, priv->ddrphy + DDRPHY_PLL1);
writel(0x0, priv->ddrphy + DDRPHY_PLL2);
writel(0x666008, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
writel(0x80666008, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
writel(0x80666008, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
writel(0x400, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
writel(0x20400, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
writel(0x20400, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL9);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_PLL11);
writel(0xf7f, priv->ddrphy + DDRPHY_SHU1_PLL0);
writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL8);
writel(0x40000, priv->ddrphy + DDRPHY_SHU1_PLL10);
writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL4);
writel(0xe57800fe, priv->ddrphy + DDRPHY_SHU1_PLL6);
writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL5);
writel(0xB5000000, priv->ddrphy + DDRPHY_SHU1_PLL7);
writel(0x14d0002, priv->ddrphy + DDRPHY_PLL5);
writel(0x14d0002, priv->ddrphy + DDRPHY_PLL7);
writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL8);
writel(0x80040000, priv->ddrphy + DDRPHY_SHU1_PLL10);
writel(0xf, priv->ddrphy + DDRPHY_SHU1_PLL1);
writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
writel(0x698600, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
writel(0xc0778600, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
writel(0xc0778600, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI4);
writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI4);
writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI4);
writel(0x2ba800, priv->ddrphy + DDRPHY_CA_DLL_ARPI1);
writel(0x2ae806, priv->ddrphy + DDRPHY_B0_DLL_ARPI1);
writel(0xae806, priv->ddrphy + DDRPHY_B1_DLL_ARPI1);
writel(0xba000, priv->ddrphy + DDRPHY_CA_DLL_ARPI3);
writel(0x2e800, priv->ddrphy + DDRPHY_B0_DLL_ARPI3);
writel(0x2e800, priv->ddrphy + DDRPHY_B1_DLL_ARPI3);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_CA_CMD4);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_B0_DQ4);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_B1_DQ4);
writel(0x4, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
writel(0x1, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
writel(0x1, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
writel(0x32cf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
writel(0x32cd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
writel(0x80010000, priv->ddrphy + DDRPHY_PLL1);
writel(0x80000000, priv->ddrphy + DDRPHY_PLL2);
udelay(100);
writel(0xc, priv->ddrphy + DDRPHY_CA_DLL_ARPI0);
writel(0x9, priv->ddrphy + DDRPHY_B0_DLL_ARPI0);
writel(0x9, priv->ddrphy + DDRPHY_B1_DLL_ARPI0);
writel(0xd0000, priv->ddrphy + DDRPHY_PLL4);
udelay(1);
writel(0x82, priv->ddrphy + DDRPHY_MISC_CTRL1);
writel(0x2, priv->dramc_ao + DRAMC_DDRCONF0);
writel(0x3acf0000, priv->ddrphy + DDRPHY_SHU1_CA_CMD6);
writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B0_DQ6);
writel(0x3acd0000, priv->ddrphy + DDRPHY_SHU1_B1_DQ6);
udelay(1);
writel(0x0, priv->ddrphy + DDRPHY_CA_DLL_ARPI2);
writel(0x0, priv->ddrphy + DDRPHY_B0_DLL_ARPI2);
writel(0x0, priv->ddrphy + DDRPHY_B1_DLL_ARPI2);
writel(0x80, priv->ddrphy + DDRPHY_MISC_CTRL1);
writel(0x0, priv->dramc_ao + DRAMC_DDRCONF0);
writel(0x80000000, priv->ddrphy + DDRPHY_PLL1);
udelay(1);
writel(0x698e00, priv->ddrphy + DDRPHY_CA_DLL_ARPI5);
udelay(1);
writel(0xc0778e00, priv->ddrphy + DDRPHY_B0_DLL_ARPI5);
udelay(1);
writel(0xc0778e00, priv->ddrphy + DDRPHY_B1_DLL_ARPI5);
udelay(1);
ret = clk_set_parent(&priv->mem, &priv->mem_mux);
if (ret)
return ret;
/* DDR PHY PLL setting */
writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
writel(0x51e, priv->ddrphy + DDRPHY_B1_DQ3);
writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
writel(0x80101, priv->ddrphy + DDRPHY_CA_CMD8);
writel(0x100, priv->ddrphy + DDRPHY_CA_CMD7);
writel(0x0, priv->ddrphy + DDRPHY_CA_CMD7);
writel(0x0, priv->ddrphy + DDRPHY_B0_DQ7);
writel(0x0, priv->ddrphy + DDRPHY_B1_DQ7);
writel(0x51e, priv->ddrphy + DDRPHY_B0_DQ3);
writel(0xff051e, priv->ddrphy + DDRPHY_B1_DQ3);
writel(0x0, priv->ddrphy + DDRPHY_B0_DQ2);
writel(0x1ff, priv->ddrphy + DDRPHY_B1_DQ2);
/* Update initial setting */
writel(0x5fc, priv->ddrphy + DDRPHY_B0_DQ3);
writel(0xff05fc, priv->ddrphy + DDRPHY_B1_DQ3);
writel(0x10c12d9, priv->ddrphy + DDRPHY_B0_DQ6);
writel(0x10c12d9, priv->ddrphy + DDRPHY_B1_DQ6);
writel(0xc0259, priv->ddrphy + DDRPHY_CA_CMD6);
writel(0x4000, priv->ddrphy + DDRPHY_B0_DQ2);
writel(0x41ff, priv->ddrphy + DDRPHY_B1_DQ2);
writel(0x0, priv->ddrphy + DDRPHY_B0_DQ8);
writel(0x100, priv->ddrphy + DDRPHY_B1_DQ8);
writel(0x3110e0e, priv->ddrphy + DDRPHY_B0_DQ5);
writel(0x3110e0e, priv->ddrphy + DDRPHY_B1_DQ5);
writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B0_DQ5);
writel(0x51060e, priv->ddrphy + DDRPHY_SHU1_B1_DQ5);
writel(0x39eff6, priv->dramc_ao + DRAMC_SHU_SCINTV);
writel(0x204ffff, priv->dramc_ao + DRAMC_CLKAR);
writel(0x31b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0x0, priv->dramc_ao + DRAMC_PERFCTL0);
writel(0x80000, priv->dramc_ao + DRAMC_PERFCTL0);
/* Dramc setting PC3 */
writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
writel(0x200600, priv->dramc_ao + DRAMC_SHU_DQSG_RETRY);
writel(0x101d007, priv->dramc_ao + DRAMC_SHUCTRL2);
writel(0xe090601, priv->dramc_ao + DRAMC_DVFSDLL);
writel(0x20003000, priv->dramc_ao + DRAMC_DDRCONF0);
writel(0x3900020f, priv->ddrphy + DDRPHY_MISC_CTRL0);
writel(0xa20810bf, priv->dramc_ao + DRAMC_SHU_CONF0);
writel(0x30050, priv->dramc_ao + DRAMC_SHU_ODTCTRL);
writel(0x25712000, priv->dramc_ao + DRAMC_REFCTRL0);
writel(0xb0100000, priv->dramc_ao + DRAMC_STBCAL);
writel(0x8000000, priv->dramc_ao + DRAMC_SREFCTRL);
writel(0xc0000000, priv->dramc_ao + DRAMC_SHU_PIPE);
writel(0x731004, priv->dramc_ao + DRAMC_RKCFG);
writel(0x8007320f, priv->dramc_ao + DRAMC_SHU_CONF2);
writel(0x2a7c0, priv->dramc_ao + DRAMC_SHU_SCINTV);
writel(0xc110, priv->dramc_ao + DRAMC_SHUCTRL);
writel(0x30000700, priv->dramc_ao + DRAMC_REFCTRL1);
writel(0x6543b321, priv->dramc_ao + DRAMC_REFRATRE_FILTER);
/* Update PCDDR3 default setting */
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA1);
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA2);
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA3);
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA4);
writel(0x10000111, priv->dramc_ao + DRAMC_SHU_SELPH_CA5);
writel(0x1000000, priv->dramc_ao + DRAMC_SHU_SELPH_CA6);
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA7);
writel(0x0, priv->dramc_ao + DRAMC_SHU_SELPH_CA8);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_CA_CMD9);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_CA_CMD9);
writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
writel(0x33331111, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
writel(0x33331111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ0);
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ1);
writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ2);
writel(0x33331111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQ3);
writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ7);
writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
writel(0xf0f00, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ7);
writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN0);
writel(0x0, priv->dramc_ao + DRAMC_SHURK0_SELPH_ODTEN1);
writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN0);
writel(0x0, priv->dramc_ao + DRAMC_SHURK1_SELPH_ODTEN1);
writel(0x0, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN0);
writel(0x66666666, priv->dramc_ao + DRAMC_SHURK2_SELPH_ODTEN1);
writel(0x2c000b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
writel(0x11111111, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
writel(0x64646464, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
writel(0x11111111, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG0);
writel(0x64646464, priv->dramc_ao + DRAMC_SHURK1_SELPH_DQSG1);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ6);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ2);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ3);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ4);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ5);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B0_DQ6);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ6);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ2);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ3);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ4);
writel(0xc0c0c0c, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ5);
writel(0x0, priv->ddrphy + DDRPHY_SHU1_R1_B1_DQ6);
writel(0x20000001, priv->dramc_ao + DRAMC_SHU_RANKCTL);
writel(0x2, priv->dramc_ao + DRAMC_SHURK0_DQSCTL);
writel(0x2, priv->dramc_ao + DRAMC_SHURK1_DQSCTL);
writel(0x4020b07, priv->dramc_ao + DRAMC_SHU_ACTIM0);
writel(0xb060400, priv->dramc_ao + DRAMC_SHU_ACTIM1);
writel(0x8090200, priv->dramc_ao + DRAMC_SHU_ACTIM2);
writel(0x810018, priv->dramc_ao + DRAMC_SHU_ACTIM3);
writel(0x1e9700ff, priv->dramc_ao + DRAMC_SHU_ACTIM4);
writel(0x1000908, priv->dramc_ao + DRAMC_SHU_ACTIM5);
writel(0x801040b, priv->dramc_ao + DRAMC_SHU_ACTIM_XRT);
writel(0x20000D1, priv->dramc_ao + DRAMC_SHU_AC_TIME_05T);
writel(0x80010000, priv->ddrphy + DDRPHY_PLL2);
udelay(500);
writel(0x81080000, priv->dramc_ao + DRAMC_MISCTL0);
writel(0xacf13, priv->dramc_ao + DRAMC_PERFCTL0);
writel(0xacf12, priv->dramc_ao + DRAMC_PERFCTL0);
writel(0x80, priv->dramc_ao + DRAMC_ARBCTL);
writel(0x9, priv->dramc_ao + DRAMC_PADCTRL);
writel(0x80000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
writel(0x3000000c, priv->dramc_ao + DRAMC_CLKCTRL);
writel(0x25714001, priv->dramc_ao + DRAMC_REFCTRL0);
writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0x4300000, priv->dramc_ao + DRAMC_CATRAINING1);
writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
writel(0x731414, priv->dramc_ao + DRAMC_RKCFG);
writel(0x733414, priv->dramc_ao + DRAMC_RKCFG);
udelay(20);
writel(0x80002050, priv->dramc_ao + DRAMC_CKECTRL);
udelay(100);
writel(0x400000, priv->dramc_ao + DRAMC_MRS);
writel(0x401800, priv->dramc_ao + DRAMC_MRS);
writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
udelay(100);
writel(0x601800, priv->dramc_ao + DRAMC_MRS);
writel(0x600000, priv->dramc_ao + DRAMC_MRS);
writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
udelay(100);
writel(0x200000, priv->dramc_ao + DRAMC_MRS);
writel(0x200400, priv->dramc_ao + DRAMC_MRS);
writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
udelay(100);
writel(0x400, priv->dramc_ao + DRAMC_MRS);
writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
udelay(100);
writel(0x702201, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0x10, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
writel(0x20, priv->dramc_ao + DRAMC_SPCMD);
writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
writel(0x1, priv->dramc_ao + DRAMC_HW_MRR_FUN);
writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0x702301, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
writel(0xff0000, priv->dramc_ao + DRAMC_SHU_CONF3);
writel(0x15b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0x2cb00b0f, priv->dramc_ao + DRAMC_SHU_CONF1);
writel(0x65714001, priv->dramc_ao + DRAMC_REFCTRL0);
writel(0x48000000, priv->dramc_ao + DRAMC_SREFCTRL);
writel(0xc0000107, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
writel(0x15e00, priv->dramc_ao + DRAMC_STBCAL1);
writel(0x100000, priv->dramc_ao + DRAMC_TEST2_1);
writel(0x4000, priv->dramc_ao + DRAMC_TEST2_2);
writel(0x12000480, priv->dramc_ao + DRAMC_TEST2_3);
writel(0x301d007, priv->dramc_ao + DRAMC_SHUCTRL2);
writel(0x4782321, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0x30210000, priv->dramc_ao + DRAMC_SHU_CKECTRL);
writel(0x20000, priv->dramc_ao + DRAMC_DUMMY_RD);
writel(0x4080110d, priv->dramc_ao + DRAMC_TEST2_4);
writel(0x30000721, priv->dramc_ao + DRAMC_REFCTRL1);
writel(0x0, priv->dramc_ao + DRAMC_RSTMASK);
writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0x80002000, priv->dramc_ao + DRAMC_CKECTRL);
writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
/* Apply config before calibration */
writel(0x120, priv->dramc_ao + DRAMC_DRAMC_PD_CTRL);
writel(0x11351131, priv->ddrphy + DDRPHY_MISC_CTRL3);
writel(0xffffffff, priv->ddrphy + DDRPHY_MISC_CG_CTRL0);
writel(0x2a7fe, priv->dramc_ao + DRAMC_SHU_SCINTV);
writel(0xff01ff, priv->dramc_ao + DRAMC_SHU_CONF3);
writel(0x4782320, priv->dramc_ao + DRAMC_DRAMCTRL);
writel(0xa56, priv->dramc_ao + DRAMC_ZQCS);
writel(0x80000000, priv->dramc_ao + DRAMC_SHU1_WODT);
writel(0x21, priv->ddrphy + DDRPHY_SHU1_B0_DQ7);
writel(0x1, priv->ddrphy + DDRPHY_SHU1_B1_DQ7);
writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0x35b1f1cf, priv->dramc_ao + DRAMC_SPCMDCTRL);
writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
writel(0x10002, priv->dramc_ao + DRAMC_EYESCAN);
writel(0x8100008c, priv->ddrphy + DDRPHY_MISC_CTRL1);
writel(0x45714001, priv->dramc_ao + DRAMC_REFCTRL0);
writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
writel(0xb0300000, priv->dramc_ao + DRAMC_STBCAL);
/* Write leveling */
writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
writel(0x33221100, priv->dramc_ao + DRAMC_SHU_SELPH_DQS1);
writel(0x11112222, priv->dramc_ao + DRAMC_SHU_SELPH_DQS0);
/* RX dqs gating cal */
writel(0x11111010, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG0);
writel(0x20201717, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQSG1);
writel(0x1d1f, priv->dramc_ao + DRAMC_SHURK0_DQSIEN);
/* RX window per-bit cal */
writel(0x03030404, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ2);
writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ3);
writel(0x01010303, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ4);
writel(0x01010000, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ5);
writel(0x03030606, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ2);
writel(0x02020202, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ3);
writel(0x04040303, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ4);
writel(0x06060101, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ5);
/* RX datlat cal */
writel(0x28b00a0e, priv->dramc_ao + DRAMC_SHU_CONF1);
/* TX window per-byte with 2UI cal */
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ0);
writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ2);
writel(0x11112222, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ1);
writel(0x22220000, priv->dramc_ao + DRAMC_SHURK0_SELPH_DQ3);
writel(0x1f2e2e00, priv->ddrphy + DDRPHY_SHU1_R0_B0_DQ7);
writel(0x202f2f00, priv->ddrphy + DDRPHY_SHU1_R0_B1_DQ7);
return mtk_ddr3_rank_size_detect(dev);
}