static ulong rk3568_clk_set_rate()

in drivers/clk/rockchip/clk_rk3568.c [2489:2669]

• 178 lines of code
• 86 McCabe index (conditional complexity)

static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk3568_clk_priv *priv = dev_get_priv(clk->dev);
	ulong ret = 0;

	if (!priv->gpll_hz) {
		printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
		return -ENOENT;
	}

	switch (clk->id) {
	case PLL_APLL:
	case ARMCLK:
		if (priv->armclk_hz)
			rk3568_armclk_set_clk(priv, rate);
		priv->armclk_hz = rate;
		break;
	case PLL_CPLL:
		ret = rockchip_pll_set_rate(&rk3568_pll_clks[CPLL], priv->cru,
					    CPLL, rate);
		priv->cpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[CPLL],
						      priv->cru, CPLL);
		break;
	case PLL_GPLL:
		ret = rockchip_pll_set_rate(&rk3568_pll_clks[GPLL], priv->cru,
					    GPLL, rate);
		priv->gpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[GPLL],
						      priv->cru, GPLL);
		break;
	case PLL_NPLL:
		ret = rockchip_pll_set_rate(&rk3568_pll_clks[NPLL], priv->cru,
					    NPLL, rate);
		break;
	case PLL_VPLL:
		ret = rockchip_pll_set_rate(&rk3568_pll_clks[VPLL], priv->cru,
					    VPLL, rate);
		priv->vpll_hz = rockchip_pll_get_rate(&rk3568_pll_clks[VPLL],
						      priv->cru,
						      VPLL);
		break;
	case ACLK_BUS:
	case PCLK_BUS:
	case PCLK_WDT_NS:
		ret = rk3568_bus_set_clk(priv, clk->id, rate);
		break;
	case ACLK_PERIMID:
	case HCLK_PERIMID:
		ret = rk3568_perimid_set_clk(priv, clk->id, rate);
		break;
	case ACLK_TOP_HIGH:
	case ACLK_TOP_LOW:
	case HCLK_TOP:
	case PCLK_TOP:
		ret = rk3568_top_set_clk(priv, clk->id, rate);
		break;
	case CLK_I2C1:
	case CLK_I2C2:
	case CLK_I2C3:
	case CLK_I2C4:
	case CLK_I2C5:
		ret = rk3568_i2c_set_clk(priv, clk->id, rate);
		break;
	case CLK_SPI0:
	case CLK_SPI1:
	case CLK_SPI2:
	case CLK_SPI3:
		ret = rk3568_spi_set_clk(priv, clk->id, rate);
		break;
	case CLK_PWM1:
	case CLK_PWM2:
	case CLK_PWM3:
		ret = rk3568_pwm_set_clk(priv, clk->id, rate);
		break;
	case CLK_SARADC:
	case CLK_TSADC_TSEN:
	case CLK_TSADC:
		ret = rk3568_adc_set_clk(priv, clk->id, rate);
		break;
	case HCLK_SDMMC0:
	case CLK_SDMMC0:
	case CLK_SDMMC1:
	case CLK_SDMMC2:
		ret = rk3568_sdmmc_set_clk(priv, clk->id, rate);
		break;
	case SCLK_SFC:
		ret = rk3568_sfc_set_clk(priv, rate);
		break;
	case NCLK_NANDC:
		ret = rk3568_nand_set_clk(priv, rate);
		break;
	case CCLK_EMMC:
		ret = rk3568_emmc_set_clk(priv, rate);
		break;
	case BCLK_EMMC:
		ret = rk3568_emmc_set_bclk(priv, rate);
		break;
#ifndef CONFIG_SPL_BUILD
	case ACLK_VOP:
		ret = rk3568_aclk_vop_set_clk(priv, rate);
		break;
	case DCLK_VOP0:
	case DCLK_VOP1:
	case DCLK_VOP2:
		ret = rk3568_dclk_vop_set_clk(priv, clk->id, rate);
		break;
	case SCLK_GMAC0:
	case CLK_MAC0_2TOP:
	case CLK_MAC0_REFOUT:
		ret = rk3568_gmac_src_set_clk(priv, 0, rate);
		break;
	case CLK_MAC0_OUT:
		ret = rk3568_gmac_out_set_clk(priv, 0, rate);
		break;
	case SCLK_GMAC0_RX_TX:
		ret = rk3568_gmac_tx_rx_set_clk(priv, 0, rate);
		break;
	case CLK_GMAC0_PTP_REF:
		ret = rk3568_gmac_ptp_ref_set_clk(priv, 0, rate);
		break;
	case SCLK_GMAC1:
	case CLK_MAC1_2TOP:
	case CLK_MAC1_REFOUT:
		ret = rk3568_gmac_src_set_clk(priv, 1, rate);
		break;
	case CLK_MAC1_OUT:
		ret = rk3568_gmac_out_set_clk(priv, 1, rate);
		break;
	case SCLK_GMAC1_RX_TX:
		ret = rk3568_gmac_tx_rx_set_clk(priv, 1, rate);
		break;
	case CLK_GMAC1_PTP_REF:
		ret = rk3568_gmac_ptp_ref_set_clk(priv, 1, rate);
		break;
	case DCLK_EBC:
		ret = rk3568_ebc_set_clk(priv, rate);
		break;
	case ACLK_RKVDEC_PRE:
	case ACLK_RKVDEC:
	case CLK_RKVDEC_CORE:
		ret = rk3568_rkvdec_set_clk(priv, clk->id, rate);
		break;
	case TCLK_WDT_NS:
		ret = OSC_HZ;
		break;
	case SCLK_UART1:
	case SCLK_UART2:
	case SCLK_UART3:
	case SCLK_UART4:
	case SCLK_UART5:
	case SCLK_UART6:
	case SCLK_UART7:
	case SCLK_UART8:
	case SCLK_UART9:
		ret = rk3568_uart_set_rate(priv, clk->id, rate);
		break;
#endif
	case ACLK_SECURE_FLASH:
	case ACLK_CRYPTO_NS:
	case HCLK_SECURE_FLASH:
	case HCLK_CRYPTO_NS:
	case CLK_CRYPTO_NS_RNG:
	case CLK_CRYPTO_NS_CORE:
	case CLK_CRYPTO_NS_PKA:
		ret = rk3568_crypto_set_rate(priv, clk->id, rate);
		break;
	case CPLL_500M:
	case CPLL_333M:
	case CPLL_250M:
	case CPLL_125M:
	case CPLL_100M:
	case CPLL_62P5M:
	case CPLL_50M:
	case CPLL_25M:
		ret = rk3568_cpll_div_set_rate(priv, clk->id, rate);
		break;
	default:
		return -ENOENT;
	}

	return ret;
};