in drivers/ddr/marvell/axp/ddr3_hw_training.c [79:484]
int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass,
u32 scrub_offs, u32 scrub_size, int dqs_clk_aligned,
int debug_mode, int reg_dimm_skip_wl)
{
/* A370 has no PBS mechanism */
__maybe_unused u32 first_loop_flag = 0;
u32 freq, reg;
MV_DRAM_INFO dram_info;
int ratio_2to1 = 0;
int tmp_ratio = 1;
int status;
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n");
memset(&dram_info, 0, sizeof(dram_info));
dram_info.num_cs = ddr3_get_cs_num_from_reg();
dram_info.cs_ena = ddr3_get_cs_ena_from_reg();
dram_info.target_frequency = target_freq;
dram_info.ddr_width = ddr_width;
dram_info.num_of_std_pups = ddr_width / PUP_SIZE;
dram_info.rl400_bug = 0;
dram_info.multi_cs_mr_support = 0;
#ifdef MV88F67XX
dram_info.rl400_bug = 1;
#endif
/* Ignore ECC errors - if ECC is enabled */
reg = reg_read(REG_SDRAM_CONFIG_ADDR);
if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) {
dram_info.ecc_ena = 1;
reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
reg_write(REG_SDRAM_CONFIG_ADDR, reg);
} else {
dram_info.ecc_ena = 0;
}
reg = reg_read(REG_SDRAM_CONFIG_ADDR);
if (reg & (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS))
dram_info.reg_dimm = 1;
else
dram_info.reg_dimm = 0;
dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena;
/* Get target 2T value */
reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) &
REG_DUNIT_CTRL_LOW_2T_MASK;
/* Get target CL value */
#ifdef MV88F67XX
reg = reg_read(REG_DDR3_MR0_ADDR) >> 2;
#else
reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2;
#endif
reg = (((reg >> 1) & 0xE) | (reg & 0x1)) & 0xF;
dram_info.cl = ddr3_valid_cl_to_cl(reg);
/* Get target CWL value */
#ifdef MV88F67XX
reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
#else
reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
#endif
reg &= REG_DDR3_MR2_CWL_MASK;
dram_info.cwl = reg;
#if !defined(MV88F67XX)
/* A370 has no PBS mechanism */
#if defined(MV88F78X60)
if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs))
first_loop_flag = 1;
#else
/* first_loop_flag = 1; skip mid freq at ALP/A375 */
if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs) &&
(mv_ctrl_revision_get() >= UMC_A0))
first_loop_flag = 1;
else
first_loop_flag = 0;
#endif
#endif
freq = dram_info.target_frequency;
/* Set ODT to always on */
ddr3_odt_activate(1);
/* Init XOR */
mv_sys_xor_init(&dram_info);
/* Get DRAM/HCLK ratio */
if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
ratio_2to1 = 1;
/*
* Xor Bypass - ECC support in AXP is currently available for 1:1
* modes frequency modes.
* Not all frequency modes support the ddr3 training sequence
* (Only 1200/300).
* Xor Bypass allows using the Xor initializations and scrubbing
* inside the ddr3 training sequence without running the training
* itself.
*/
if (xor_bypass == 0) {
if (ddr3_run_pbs) {
DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n");
} else {
DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n");
}
if (dram_info.target_frequency > DFS_MARGIN) {
tmp_ratio = 0;
freq = DDR_100;
if (dram_info.reg_dimm == 1)
freq = DDR_300;
if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) {
/* Set low - 100Mhz DDR Frequency by HW */
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n");
return MV_DDR3_TRAINING_ERR_DFS_H2L;
}
if ((dram_info.reg_dimm == 1) &&
(reg_dimm_skip_wl == 0)) {
if (MV_OK !=
ddr3_write_leveling_hw_reg_dimm(freq,
&dram_info))
DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n");
}
if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
ddr3_print_freq(freq);
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 2\n");
} else {
if (!dqs_clk_aligned) {
#ifdef MV88F67XX
/*
* If running training sequence without DFS,
* we must run Write leveling before writing
* the patterns
*/
/*
* ODT - Multi CS system use SW WL,
* Single CS System use HW WL
*/
if (dram_info.cs_ena > 1) {
if (MV_OK !=
ddr3_write_leveling_sw(
freq, tmp_ratio,
&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
}
} else {
if (MV_OK !=
ddr3_write_leveling_hw(freq,
&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
}
}
#else
if (MV_OK != ddr3_write_leveling_hw(
freq, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
if (ddr3_sw_wl_rl_debug) {
if (MV_OK !=
ddr3_write_leveling_sw(
freq, tmp_ratio,
&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
}
} else {
return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
}
}
#endif
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 3\n");
}
if (MV_OK != ddr3_load_patterns(&dram_info, 0)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Loading Patterns)\n");
return MV_DDR3_TRAINING_ERR_LOAD_PATTERNS;
}
/*
* TODO:
* The mainline U-Boot port of the bin_hdr DDR training code
* needs a delay of minimum 20ms here (10ms is a bit too short
* and the CPU hangs). The bin_hdr code doesn't have this delay.
* To be save here, lets add a delay of 50ms here.
*
* Tested on the Marvell DB-MV784MP-GP board
*/
mdelay(50);
do {
freq = dram_info.target_frequency;
tmp_ratio = ratio_2to1;
DEBUG_MAIN_FULL_S("DDR3 Training Sequence - DEBUG - 4\n");
#if defined(MV88F78X60)
/*
* There is a difference on the DFS frequency at the
* first iteration of this loop
*/
if (first_loop_flag) {
freq = DDR_400;
tmp_ratio = 0;
}
#endif
if (MV_OK != ddr3_dfs_low_2_high(freq, tmp_ratio,
&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs Low2High)\n");
return MV_DDR3_TRAINING_ERR_DFS_H2L;
}
if (ddr3_get_log_level() >= MV_LOG_LEVEL_1) {
ddr3_print_freq(freq);
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 5\n");
/* Write leveling */
if (!dqs_clk_aligned) {
#ifdef MV88F67XX
/*
* ODT - Multi CS system that not support Multi
* CS MRS commands must use SW WL
*/
if (dram_info.cs_ena > 1) {
if (MV_OK != ddr3_write_leveling_sw(
freq, tmp_ratio, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
}
} else {
if (MV_OK != ddr3_write_leveling_hw(
freq, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
}
}
#else
if ((dram_info.reg_dimm == 1) &&
(freq == DDR_400)) {
if (reg_dimm_skip_wl == 0) {
if (MV_OK != ddr3_write_leveling_hw_reg_dimm(
freq, &dram_info))
DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM WL - SKIP\n");
}
} else {
if (MV_OK != ddr3_write_leveling_hw(
freq, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hw)\n");
if (ddr3_sw_wl_rl_debug) {
if (MV_OK != ddr3_write_leveling_sw(
freq, tmp_ratio, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
}
} else {
return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
}
}
}
#endif
if (debug_mode)
DEBUG_MAIN_S
("DDR3 Training Sequence - DEBUG - 6\n");
}
/* Read Leveling */
/*
* Armada 370 - Support for HCLK @ 400MHZ - must use
* SW read leveling
*/
if (freq == DDR_400 && dram_info.rl400_bug) {
status = ddr3_read_leveling_sw(freq, tmp_ratio,
&dram_info);
if (MV_OK != status) {
DEBUG_MAIN_S
("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n");
return status;
}
} else {
if (MV_OK != ddr3_read_leveling_hw(
freq, &dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Hw)\n");
if (ddr3_sw_wl_rl_debug) {
if (MV_OK != ddr3_read_leveling_sw(
freq, tmp_ratio,
&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Read Leveling Sw)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_SW;
}
} else {
return MV_DDR3_TRAINING_ERR_WR_LVL_HW;
}
}
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 7\n");
if (MV_OK != ddr3_wl_supplement(&dram_info)) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Hi-Freq Sup)\n");
return MV_DDR3_TRAINING_ERR_WR_LVL_HI_FREQ;
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 8\n");
#if !defined(MV88F67XX)
/* A370 has no PBS mechanism */
#if defined(MV88F78X60) || defined(MV88F672X)
if (first_loop_flag == 1) {
first_loop_flag = 0;
status = MV_OK;
status = ddr3_pbs_rx(&dram_info);
if (MV_OK != status) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS RX)\n");
return status;
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 9\n");
status = ddr3_pbs_tx(&dram_info);
if (MV_OK != status) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (PBS TX)\n");
return status;
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 10\n");
}
#endif
#endif
} while (freq != dram_info.target_frequency);
status = ddr3_dqs_centralization_rx(&dram_info);
if (MV_OK != status) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization RX)\n");
return status;
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 11\n");
status = ddr3_dqs_centralization_tx(&dram_info);
if (MV_OK != status) {
DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (DQS Centralization TX)\n");
return status;
}
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 12\n");
}
ddr3_set_performance_params(&dram_info);
if (dram_info.ecc_ena) {
/* Need to SCRUB the DRAM memory area to load U-Boot */
mv_sys_xor_finish();
dram_info.num_cs = 1;
dram_info.cs_ena = 1;
mv_sys_xor_init(&dram_info);
mv_xor_mem_init(0, scrub_offs, scrub_size, 0xdeadbeef,
0xdeadbeef);
/* Wait for previous transfer completion */
while (mv_xor_state_get(0) != MV_IDLE)
;
if (debug_mode)
DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 13\n");
}
/* Return XOR State */
mv_sys_xor_finish();
#if defined(MV88F78X60)
/* Save training results in memeory for resume state */
ddr3_save_training(&dram_info);
#endif
/* Clear ODT always on */
ddr3_odt_activate(0);
/* Configure Dynamic read ODT */
ddr3_odt_read_dynamic_config(&dram_info);
return MV_OK;
}