in board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c [1026:1472]
static int serdes_illcalib_pcie_gen1(u32 lane3_protocol, u32 lane3_rate,
u32 lane2_protocol, u32 lane2_rate,
u32 lane1_protocol, u32 lane1_rate,
u32 lane0_protocol, u32 lane0_rate,
u32 gen2_calib)
{
u64 tempbistresult;
u32 currbistresult[4];
u32 prevbistresult[4];
u32 itercount = 0;
u32 ill12_val[4], ill1_val[4];
u32 loop = 0;
u32 iterresult[8];
u32 meancount[4];
u32 bistpasscount[4];
u32 meancountalt[4];
u32 meancountalt_bistpasscount[4];
u32 lane0_active;
u32 lane1_active;
u32 lane2_active;
u32 lane3_active;
lane0_active = (lane0_protocol == 1);
lane1_active = (lane1_protocol == 1);
lane2_active = (lane2_protocol == 1);
lane3_active = (lane3_protocol == 1);
for (loop = 0; loop <= 3; loop++) {
iterresult[loop] = 0;
iterresult[loop + 4] = 0;
meancountalt[loop] = 0;
meancountalt_bistpasscount[loop] = 0;
meancount[loop] = 0;
prevbistresult[loop] = 0;
bistpasscount[loop] = 0;
}
itercount = 0;
if (lane0_active)
serdes_bist_static_settings(0);
if (lane1_active)
serdes_bist_static_settings(1);
if (lane2_active)
serdes_bist_static_settings(2);
if (lane3_active)
serdes_bist_static_settings(3);
do {
if (gen2_calib != 1) {
if (lane0_active == 1)
ill1_val[0] = ((0x04 + itercount * 8) % 0x100);
if (lane0_active == 1)
ill12_val[0] =
((0x04 + itercount * 8) >=
0x100) ? 0x10 : 0x00;
if (lane1_active == 1)
ill1_val[1] = ((0x04 + itercount * 8) % 0x100);
if (lane1_active == 1)
ill12_val[1] =
((0x04 + itercount * 8) >=
0x100) ? 0x10 : 0x00;
if (lane2_active == 1)
ill1_val[2] = ((0x04 + itercount * 8) % 0x100);
if (lane2_active == 1)
ill12_val[2] =
((0x04 + itercount * 8) >=
0x100) ? 0x10 : 0x00;
if (lane3_active == 1)
ill1_val[3] = ((0x04 + itercount * 8) % 0x100);
if (lane3_active == 1)
ill12_val[3] =
((0x04 + itercount * 8) >=
0x100) ? 0x10 : 0x00;
if (lane0_active == 1)
Xil_Out32(0xFD401924, ill1_val[0]);
if (lane0_active == 1)
psu_mask_write(0xFD401990, 0x000000F0U,
ill12_val[0]);
if (lane1_active == 1)
Xil_Out32(0xFD405924, ill1_val[1]);
if (lane1_active == 1)
psu_mask_write(0xFD405990, 0x000000F0U,
ill12_val[1]);
if (lane2_active == 1)
Xil_Out32(0xFD409924, ill1_val[2]);
if (lane2_active == 1)
psu_mask_write(0xFD409990, 0x000000F0U,
ill12_val[2]);
if (lane3_active == 1)
Xil_Out32(0xFD40D924, ill1_val[3]);
if (lane3_active == 1)
psu_mask_write(0xFD40D990, 0x000000F0U,
ill12_val[3]);
}
if (gen2_calib == 1) {
if (lane0_active == 1)
ill1_val[0] = ((0x104 + itercount * 8) % 0x100);
if (lane0_active == 1)
ill12_val[0] =
((0x104 + itercount * 8) >=
0x200) ? 0x02 : 0x01;
if (lane1_active == 1)
ill1_val[1] = ((0x104 + itercount * 8) % 0x100);
if (lane1_active == 1)
ill12_val[1] =
((0x104 + itercount * 8) >=
0x200) ? 0x02 : 0x01;
if (lane2_active == 1)
ill1_val[2] = ((0x104 + itercount * 8) % 0x100);
if (lane2_active == 1)
ill12_val[2] =
((0x104 + itercount * 8) >=
0x200) ? 0x02 : 0x01;
if (lane3_active == 1)
ill1_val[3] = ((0x104 + itercount * 8) % 0x100);
if (lane3_active == 1)
ill12_val[3] =
((0x104 + itercount * 8) >=
0x200) ? 0x02 : 0x01;
if (lane0_active == 1)
Xil_Out32(0xFD401928, ill1_val[0]);
if (lane0_active == 1)
psu_mask_write(0xFD401990, 0x0000000FU,
ill12_val[0]);
if (lane1_active == 1)
Xil_Out32(0xFD405928, ill1_val[1]);
if (lane1_active == 1)
psu_mask_write(0xFD405990, 0x0000000FU,
ill12_val[1]);
if (lane2_active == 1)
Xil_Out32(0xFD409928, ill1_val[2]);
if (lane2_active == 1)
psu_mask_write(0xFD409990, 0x0000000FU,
ill12_val[2]);
if (lane3_active == 1)
Xil_Out32(0xFD40D928, ill1_val[3]);
if (lane3_active == 1)
psu_mask_write(0xFD40D990, 0x0000000FU,
ill12_val[3]);
}
if (lane0_active == 1)
psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U);
if (lane1_active == 1)
psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U);
if (lane2_active == 1)
psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U);
if (lane3_active == 1)
psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U);
if (lane0_active == 1)
currbistresult[0] = 0;
if (lane1_active == 1)
currbistresult[1] = 0;
if (lane2_active == 1)
currbistresult[2] = 0;
if (lane3_active == 1)
currbistresult[3] = 0;
serdes_rst_seq(lane3_protocol, lane3_rate, lane2_protocol,
lane2_rate, lane1_protocol, lane1_rate,
lane0_protocol, lane0_rate);
if (lane3_active == 1)
serdes_bist_run(3);
if (lane2_active == 1)
serdes_bist_run(2);
if (lane1_active == 1)
serdes_bist_run(1);
if (lane0_active == 1)
serdes_bist_run(0);
tempbistresult = 0;
if (lane3_active == 1)
tempbistresult = tempbistresult | serdes_bist_result(3);
tempbistresult = tempbistresult << 1;
if (lane2_active == 1)
tempbistresult = tempbistresult | serdes_bist_result(2);
tempbistresult = tempbistresult << 1;
if (lane1_active == 1)
tempbistresult = tempbistresult | serdes_bist_result(1);
tempbistresult = tempbistresult << 1;
if (lane0_active == 1)
tempbistresult = tempbistresult | serdes_bist_result(0);
Xil_Out32(0xFD410098, 0x0);
Xil_Out32(0xFD410098, 0x2);
if (itercount < 32) {
iterresult[0] =
((iterresult[0] << 1) |
((tempbistresult & 0x1) == 0x1));
iterresult[1] =
((iterresult[1] << 1) |
((tempbistresult & 0x2) == 0x2));
iterresult[2] =
((iterresult[2] << 1) |
((tempbistresult & 0x4) == 0x4));
iterresult[3] =
((iterresult[3] << 1) |
((tempbistresult & 0x8) == 0x8));
} else {
iterresult[4] =
((iterresult[4] << 1) |
((tempbistresult & 0x1) == 0x1));
iterresult[5] =
((iterresult[5] << 1) |
((tempbistresult & 0x2) == 0x2));
iterresult[6] =
((iterresult[6] << 1) |
((tempbistresult & 0x4) == 0x4));
iterresult[7] =
((iterresult[7] << 1) |
((tempbistresult & 0x8) == 0x8));
}
currbistresult[0] =
currbistresult[0] | ((tempbistresult & 0x1) == 1);
currbistresult[1] =
currbistresult[1] | ((tempbistresult & 0x2) == 0x2);
currbistresult[2] =
currbistresult[2] | ((tempbistresult & 0x4) == 0x4);
currbistresult[3] =
currbistresult[3] | ((tempbistresult & 0x8) == 0x8);
for (loop = 0; loop <= 3; loop++) {
if (currbistresult[loop] == 1 && prevbistresult[loop] == 1)
bistpasscount[loop] = bistpasscount[loop] + 1;
if (bistpasscount[loop] < 4 &&
currbistresult[loop] == 0 && itercount > 2) {
if (meancountalt_bistpasscount[loop] <
bistpasscount[loop]) {
meancountalt_bistpasscount[loop] =
bistpasscount[loop];
meancountalt[loop] =
((itercount - 1) -
((bistpasscount[loop] + 1) / 2));
}
bistpasscount[loop] = 0;
}
if (meancount[loop] == 0 && bistpasscount[loop] >= 4 &&
(currbistresult[loop] == 0 || itercount == 63) &&
prevbistresult[loop] == 1)
meancount[loop] =
(itercount - 1) -
((bistpasscount[loop] + 1) / 2);
prevbistresult[loop] = currbistresult[loop];
}
} while (++itercount < 64);
for (loop = 0; loop <= 3; loop++) {
if (lane0_active == 0 && loop == 0)
continue;
if (lane1_active == 0 && loop == 1)
continue;
if (lane2_active == 0 && loop == 2)
continue;
if (lane3_active == 0 && loop == 3)
continue;
if (meancount[loop] == 0)
meancount[loop] = meancountalt[loop];
if (gen2_calib != 1) {
ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100);
ill12_val[loop] =
((0x04 + meancount[loop] * 8) >=
0x100) ? 0x10 : 0x00;
Xil_Out32(0xFFFE0000 + loop * 4, iterresult[loop]);
Xil_Out32(0xFFFE0010 + loop * 4, iterresult[loop + 4]);
Xil_Out32(0xFFFE0020 + loop * 4, bistpasscount[loop]);
Xil_Out32(0xFFFE0030 + loop * 4, meancount[loop]);
}
if (gen2_calib == 1) {
ill1_val[loop] =
((0x104 + meancount[loop] * 8) % 0x100);
ill12_val[loop] =
((0x104 + meancount[loop] * 8) >=
0x200) ? 0x02 : 0x01;
Xil_Out32(0xFFFE0040 + loop * 4, iterresult[loop]);
Xil_Out32(0xFFFE0050 + loop * 4, iterresult[loop + 4]);
Xil_Out32(0xFFFE0060 + loop * 4, bistpasscount[loop]);
Xil_Out32(0xFFFE0070 + loop * 4, meancount[loop]);
}
}
if (gen2_calib != 1) {
if (lane0_active == 1)
Xil_Out32(0xFD401924, ill1_val[0]);
if (lane0_active == 1)
psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]);
if (lane1_active == 1)
Xil_Out32(0xFD405924, ill1_val[1]);
if (lane1_active == 1)
psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]);
if (lane2_active == 1)
Xil_Out32(0xFD409924, ill1_val[2]);
if (lane2_active == 1)
psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]);
if (lane3_active == 1)
Xil_Out32(0xFD40D924, ill1_val[3]);
if (lane3_active == 1)
psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]);
}
if (gen2_calib == 1) {
if (lane0_active == 1)
Xil_Out32(0xFD401928, ill1_val[0]);
if (lane0_active == 1)
psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]);
if (lane1_active == 1)
Xil_Out32(0xFD405928, ill1_val[1]);
if (lane1_active == 1)
psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]);
if (lane2_active == 1)
Xil_Out32(0xFD409928, ill1_val[2]);
if (lane2_active == 1)
psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]);
if (lane3_active == 1)
Xil_Out32(0xFD40D928, ill1_val[3]);
if (lane3_active == 1)
psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]);
}
if (lane0_active == 1)
psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U);
if (lane1_active == 1)
psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U);
if (lane2_active == 1)
psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U);
if (lane3_active == 1)
psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U);
Xil_Out32(0xFD410098, 0);
if (lane0_active == 1) {
Xil_Out32(0xFD403004, 0);
Xil_Out32(0xFD403008, 0);
Xil_Out32(0xFD40300C, 0);
Xil_Out32(0xFD403010, 0);
Xil_Out32(0xFD403014, 0);
Xil_Out32(0xFD403018, 0);
Xil_Out32(0xFD40301C, 0);
Xil_Out32(0xFD403020, 0);
Xil_Out32(0xFD403024, 0);
Xil_Out32(0xFD403028, 0);
Xil_Out32(0xFD40302C, 0);
Xil_Out32(0xFD403030, 0);
Xil_Out32(0xFD403034, 0);
Xil_Out32(0xFD403038, 0);
Xil_Out32(0xFD40303C, 0);
Xil_Out32(0xFD403040, 0);
Xil_Out32(0xFD403044, 0);
Xil_Out32(0xFD403048, 0);
Xil_Out32(0xFD40304C, 0);
Xil_Out32(0xFD403050, 0);
Xil_Out32(0xFD403054, 0);
Xil_Out32(0xFD403058, 0);
Xil_Out32(0xFD403068, 1);
Xil_Out32(0xFD40306C, 0);
Xil_Out32(0xFD4010AC, 0);
psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U);
psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U);
psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U);
}
if (lane1_active == 1) {
Xil_Out32(0xFD407004, 0);
Xil_Out32(0xFD407008, 0);
Xil_Out32(0xFD40700C, 0);
Xil_Out32(0xFD407010, 0);
Xil_Out32(0xFD407014, 0);
Xil_Out32(0xFD407018, 0);
Xil_Out32(0xFD40701C, 0);
Xil_Out32(0xFD407020, 0);
Xil_Out32(0xFD407024, 0);
Xil_Out32(0xFD407028, 0);
Xil_Out32(0xFD40702C, 0);
Xil_Out32(0xFD407030, 0);
Xil_Out32(0xFD407034, 0);
Xil_Out32(0xFD407038, 0);
Xil_Out32(0xFD40703C, 0);
Xil_Out32(0xFD407040, 0);
Xil_Out32(0xFD407044, 0);
Xil_Out32(0xFD407048, 0);
Xil_Out32(0xFD40704C, 0);
Xil_Out32(0xFD407050, 0);
Xil_Out32(0xFD407054, 0);
Xil_Out32(0xFD407058, 0);
Xil_Out32(0xFD407068, 1);
Xil_Out32(0xFD40706C, 0);
Xil_Out32(0xFD4050AC, 0);
psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U);
psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U);
psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U);
}
if (lane2_active == 1) {
Xil_Out32(0xFD40B004, 0);
Xil_Out32(0xFD40B008, 0);
Xil_Out32(0xFD40B00C, 0);
Xil_Out32(0xFD40B010, 0);
Xil_Out32(0xFD40B014, 0);
Xil_Out32(0xFD40B018, 0);
Xil_Out32(0xFD40B01C, 0);
Xil_Out32(0xFD40B020, 0);
Xil_Out32(0xFD40B024, 0);
Xil_Out32(0xFD40B028, 0);
Xil_Out32(0xFD40B02C, 0);
Xil_Out32(0xFD40B030, 0);
Xil_Out32(0xFD40B034, 0);
Xil_Out32(0xFD40B038, 0);
Xil_Out32(0xFD40B03C, 0);
Xil_Out32(0xFD40B040, 0);
Xil_Out32(0xFD40B044, 0);
Xil_Out32(0xFD40B048, 0);
Xil_Out32(0xFD40B04C, 0);
Xil_Out32(0xFD40B050, 0);
Xil_Out32(0xFD40B054, 0);
Xil_Out32(0xFD40B058, 0);
Xil_Out32(0xFD40B068, 1);
Xil_Out32(0xFD40B06C, 0);
Xil_Out32(0xFD4090AC, 0);
psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U);
psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U);
psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U);
}
if (lane3_active == 1) {
Xil_Out32(0xFD40F004, 0);
Xil_Out32(0xFD40F008, 0);
Xil_Out32(0xFD40F00C, 0);
Xil_Out32(0xFD40F010, 0);
Xil_Out32(0xFD40F014, 0);
Xil_Out32(0xFD40F018, 0);
Xil_Out32(0xFD40F01C, 0);
Xil_Out32(0xFD40F020, 0);
Xil_Out32(0xFD40F024, 0);
Xil_Out32(0xFD40F028, 0);
Xil_Out32(0xFD40F02C, 0);
Xil_Out32(0xFD40F030, 0);
Xil_Out32(0xFD40F034, 0);
Xil_Out32(0xFD40F038, 0);
Xil_Out32(0xFD40F03C, 0);
Xil_Out32(0xFD40F040, 0);
Xil_Out32(0xFD40F044, 0);
Xil_Out32(0xFD40F048, 0);
Xil_Out32(0xFD40F04C, 0);
Xil_Out32(0xFD40F050, 0);
Xil_Out32(0xFD40F054, 0);
Xil_Out32(0xFD40F058, 0);
Xil_Out32(0xFD40F068, 1);
Xil_Out32(0xFD40F06C, 0);
Xil_Out32(0xFD40D0AC, 0);
psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U);
psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U);
psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U);
}
return 1;
}