in drivers/ddr/marvell/a38x/ddr3_training.c [2008:2467]
static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
{
/* TODO: enable this functionality for other platforms */
struct init_cntr_param init_cntr_prm;
int ret = MV_OK;
int adll_bypass_flag = 0;
u32 if_id;
unsigned int max_cs = mv_ddr_cs_num_get();
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
enum mv_ddr_freq freq = tm->interface_params[0].memory_freq;
unsigned int *freq_tbl = mv_ddr_freq_tbl_get();
#ifdef DDR_VIEWER_TOOL
if (debug_training == DEBUG_LEVEL_TRACE) {
CHECK_STATUS(print_device_info((u8)dev_num));
}
#endif
ddr3_tip_validate_algo_components(dev_num);
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
freq_tbl[MV_DDR_FREQ_LOW_FREQ] = dfs_low_freq;
if (is_pll_before_init != 0) {
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
config_func_info[dev_num].tip_set_freq_divider_func(
(u8)dev_num, if_id, freq);
}
}
/* TODO: enable this functionality for other platforms */
if (is_adll_calib_before_init != 0) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("with adll calib before init\n"));
adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
}
if (is_reg_dump != 0) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("Dump before init controller\n"));
ddr3_tip_reg_dump(dev_num);
}
if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
training_stage = INIT_CONTROLLER;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("INIT_CONTROLLER_MASK_BIT\n"));
init_cntr_prm.do_mrs_phy = 1;
init_cntr_prm.is_ctrl64_bit = 0;
init_cntr_prm.init_phy = 1;
init_cntr_prm.msys_init = 0;
ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("hws_ddr3_tip_init_controller failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("adll_calibration failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
training_stage = SET_LOW_FREQ;
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f);
adll_bypass_flag = 1;
}
effective_cs = 0;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("SET_LOW_FREQ_MASK_BIT %d\n",
freq_tbl[low_freq]));
ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, low_freq);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_freq_set failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & WRITE_LEVELING_LF_MASK_BIT) {
training_stage = WRITE_LEVELING_LF;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("WRITE_LEVELING_LF_MASK_BIT\n"));
ret = ddr3_tip_dynamic_write_leveling(dev_num, 1);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_write_leveling LF failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
training_stage = LOAD_PATTERN;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("LOAD_PATTERN_MASK_BIT #%d\n",
effective_cs));
ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
if (adll_bypass_flag == 1) {
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0);
adll_bypass_flag = 0;
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
training_stage = SET_MEDIUM_FREQ;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("SET_MEDIUM_FREQ_MASK_BIT %d\n",
freq_tbl[medium_freq]));
ret =
ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE, medium_freq);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_freq_set failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
training_stage = WRITE_LEVELING;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("WRITE_LEVELING_MASK_BIT\n"));
if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
} else {
/* Use old WL */
ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
}
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_write_leveling failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
training_stage = LOAD_PATTERN_2;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("LOAD_PATTERN_2_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_load_all_pattern_to_mem failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
if (mask_tune_func & READ_LEVELING_MASK_BIT) {
training_stage = READ_LEVELING;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("READ_LEVELING_MASK_BIT\n"));
if ((rl_mid_freq_wa == 0) || (freq_tbl[medium_freq] == 533)) {
ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
} else {
/* Use old RL */
ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
}
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_read_leveling failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
training_stage = WRITE_LEVELING_SUPP;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("WRITE_LEVELING_SUPP_MASK_BIT\n"));
ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_write_leveling_supp failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & PBS_RX_MASK_BIT) {
training_stage = PBS_RX;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("PBS_RX_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_pbs_rx(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_pbs_rx failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & PBS_TX_MASK_BIT) {
training_stage = PBS_TX;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("PBS_TX_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_pbs_tx(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_pbs_tx failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
training_stage = SET_TARGET_FREQ;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("SET_TARGET_FREQ_MASK_BIT %d\n",
freq_tbl[tm->
interface_params[first_active_if].
memory_freq]));
ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
PARAM_NOT_CARE,
tm->interface_params[first_active_if].
memory_freq);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_freq_set failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
training_stage = WRITE_LEVELING_TF;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("WRITE_LEVELING_TF_MASK_BIT\n"));
ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_write_leveling TF failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & LOAD_PATTERN_HIGH_MASK_BIT) {
training_stage = LOAD_PATTERN_HIGH;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("LOAD_PATTERN_HIGH\n"));
ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_load_all_pattern_to_mem failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
training_stage = READ_LEVELING_TF;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("READ_LEVELING_TF_MASK_BIT\n"));
ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
interface_params[first_active_if].
memory_freq);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_read_leveling TF failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & RL_DQS_BURST_MASK_BIT) {
training_stage = READ_LEVELING_TF;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("RL_DQS_BURST_MASK_BIT\n"));
ret = mv_ddr_rl_dqs_burst(0, 0, tm->interface_params[0].memory_freq);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("mv_ddr_rl_dqs_burst TF failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
if (mask_tune_func & DM_PBS_TX_MASK_BIT) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_PBS_TX_MASK_BIT\n"));
}
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
training_stage = VREF_CALIBRATION;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("VREF\n"));
ret = ddr3_tip_vref(dev_num);
if (is_reg_dump != 0) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("VREF Dump\n"));
ddr3_tip_reg_dump(dev_num);
}
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_vref failure\n"));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
training_stage = CENTRALIZATION_RX;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("CENTRALIZATION_RX_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_centralization_rx(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_centralization_rx failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
training_stage = WRITE_LEVELING_SUPP_TF;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("WRITE_LEVELING_SUPP_TF_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_dynamic_write_leveling_supp TF failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
for (effective_cs = 0; effective_cs < max_cs; effective_cs++) {
if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
training_stage = CENTRALIZATION_TX;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
("CENTRALIZATION_TX_MASK_BIT CS #%d\n",
effective_cs));
ret = ddr3_tip_centralization_tx(dev_num);
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
if (ret != MV_OK) {
DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
("ddr3_tip_centralization_tx failure CS #%d\n",
effective_cs));
if (debug_mode == 0)
return MV_FAIL;
}
}
}
/* Set to 0 after each loop to avoid illegal value may be used */
effective_cs = 0;
DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("restore registers to default\n"));
/* restore register values */
CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
if (is_reg_dump != 0)
ddr3_tip_reg_dump(dev_num);
return MV_OK;
}