inline static uint32_t midr_score_core()

in src/arm/midr.h [171:232]

• 51 lines of code
• 34 McCabe index (conditional complexity)

inline static uint32_t midr_score_core(uint32_t midr) {
	const uint32_t core_mask = CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK;
	switch (midr & core_mask) {
		case UINT32_C(0x53000030): /* Exynos M4 */
		case UINT32_C(0x53000040): /* Exynos M5 */
		case UINT32_C(0x4100D440): /* Cortex-X1 */
			/* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78 */
			return 6;
		case UINT32_C(0x4E000030): /* Denver 2 */
		case UINT32_C(0x53000010): /* Exynos M1 and Exynos M2 */
		case UINT32_C(0x53000020): /* Exynos M3 */
		case UINT32_C(0x51008040): /* Kryo 485 Gold / Gold Prime */
		case UINT32_C(0x51008020): /* Kryo 385 Gold */
		case UINT32_C(0x51008000): /* Kryo 260 / 280 Gold */
		case UINT32_C(0x51002050): /* Kryo Gold */
		case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */
		case UINT32_C(0x4100D410): /* Cortex-A78 */
		case UINT32_C(0x4100D0D0): /* Cortex-A77 */
		case UINT32_C(0x4100D0E0): /* Cortex-A76AE */
		case UINT32_C(0x4100D0B0): /* Cortex-A76 */
		case UINT32_C(0x4100D0A0): /* Cortex-A75 */
		case UINT32_C(0x4100D090): /* Cortex-A73 */
		case UINT32_C(0x4100D080): /* Cortex-A72 */
#if CPUINFO_ARCH_ARM
		case UINT32_C(0x4100C0F0): /* Cortex-A15 */
		case UINT32_C(0x4100C0E0): /* Cortex-A17 */
		case UINT32_C(0x4100C0D0): /* Rockchip RK3288 cores */
		case UINT32_C(0x4100C0C0): /* Cortex-A12 */
#endif /* CPUINFO_ARCH_ARM */
			/* These cores are always in big role */
			return 5;
		case UINT32_C(0x4100D070): /* Cortex-A57 */
			/* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or in big role w.r.t. Cortex-A53 */
			return 4;
#if CPUINFO_ARCH_ARM64
		case UINT32_C(0x4100D060): /* Cortex-A65 */
#endif /* CPUINFO_ARCH_ARM64 */
		case UINT32_C(0x4100D050): /* Cortex-A55 */
		case UINT32_C(0x4100D030): /* Cortex-A53 */
			/* Cortex-A53 is usually in LITTLE role, but can be in big role w.r.t. Cortex-A35 */
			return 2;
		case UINT32_C(0x4100D040): /* Cortex-A35 */
#if CPUINFO_ARCH_ARM
		case UINT32_C(0x4100C070): /* Cortex-A7 */
#endif /* CPUINFO_ARCH_ARM */
		case UINT32_C(0x51008050): /* Kryo 485 Silver */
		case UINT32_C(0x51008030): /* Kryo 385 Silver */
		case UINT32_C(0x51008010): /* Kryo 260 / 280 Silver */
		case UINT32_C(0x51002110): /* Kryo Silver (Snapdragon 820) */
		case UINT32_C(0x51002010): /* Kryo Silver (Snapdragon 821) */
			/* These cores are always in LITTLE core */
			return 1;
		default:
			/*
			 * Unknown cores, or cores which do not have big/LITTLE roles.
			 * To be future-proof w.r.t. cores not yet recognized in cpuinfo, assume position between
			 * Cortex-A57/A72/A73/A75 and Cortex-A53/A55. Then at least future cores paired with
			 * one of these known cores will be properly scored.
			 */
			return 3;
	}
}