in cores/gba/src/gb/io.c [523:621]
uint8_t GBIORead(struct GB* gb, unsigned address) {
switch (address) {
case REG_JOYP:
return _readKeys(gb);
case REG_IE:
return gb->memory.ie;
case REG_WAVE_0:
case REG_WAVE_1:
case REG_WAVE_2:
case REG_WAVE_3:
case REG_WAVE_4:
case REG_WAVE_5:
case REG_WAVE_6:
case REG_WAVE_7:
case REG_WAVE_8:
case REG_WAVE_9:
case REG_WAVE_A:
case REG_WAVE_B:
case REG_WAVE_C:
case REG_WAVE_D:
case REG_WAVE_E:
case REG_WAVE_F:
if (gb->audio.playingCh3) {
if (gb->audio.ch3.readable || gb->audio.style != GB_AUDIO_DMG) {
return gb->audio.ch3.wavedata8[gb->audio.ch3.window >> 1];
} else {
return 0xFF;
}
} else {
return gb->audio.ch3.wavedata8[address - REG_WAVE_0];
}
break;
case REG_SB:
case REG_SC:
case REG_IF:
case REG_NR10:
case REG_NR11:
case REG_NR12:
case REG_NR14:
case REG_NR21:
case REG_NR22:
case REG_NR24:
case REG_NR30:
case REG_NR32:
case REG_NR34:
case REG_NR41:
case REG_NR42:
case REG_NR43:
case REG_NR44:
case REG_NR50:
case REG_NR51:
case REG_NR52:
case REG_DIV:
case REG_TIMA:
case REG_TMA:
case REG_TAC:
case REG_STAT:
case REG_LCDC:
case REG_SCY:
case REG_SCX:
case REG_LY:
case REG_LYC:
case REG_BGP:
case REG_OBP0:
case REG_OBP1:
case REG_WY:
case REG_WX:
// Handled transparently by the registers
break;
default:
if (gb->model >= GB_MODEL_CGB) {
switch (address) {
case REG_KEY1:
case REG_VBK:
case REG_HDMA1:
case REG_HDMA2:
case REG_HDMA3:
case REG_HDMA4:
case REG_HDMA5:
case REG_BCPS:
case REG_BCPD:
case REG_OCPS:
case REG_OCPD:
case REG_SVBK:
// Handled transparently by the registers
goto success;
case REG_DMA:
mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
return 0;
default:
break;
}
}
mLOG(GB_IO, STUB, "Reading from unknown register FF%02X", address);
return 0xFF;
}
success:
return gb->memory.io[address] | _registerMask[address];
}