in dexdump/dexdump.cc [615:849]
static void dumpInstruction(const DexFile* pDexFile,
const DexFile::CodeItem* pCode,
u4 codeOffset, u4 insnIdx, u4 insnWidth,
const Instruction* pDecInsn) {
// Address of instruction (expressed as byte offset).
fprintf(gOutFile, "%06x:", codeOffset + 0x10 + insnIdx * 2);
// Dump (part of) raw bytes.
const u2* insns = pCode->insns_;
for (u4 i = 0; i < 8; i++) {
if (i < insnWidth) {
if (i == 7) {
fprintf(gOutFile, " ... ");
} else {
// Print 16-bit value in little-endian order.
const u1* bytePtr = (const u1*) &insns[insnIdx + i];
fprintf(gOutFile, " %02x%02x", bytePtr[0], bytePtr[1]);
}
} else {
fputs(" ", gOutFile);
}
} // for
// Dump pseudo-instruction or opcode.
if (pDecInsn->Opcode() == Instruction::NOP) {
const u2 instr = get2LE((const u1*) &insns[insnIdx]);
if (instr == Instruction::kPackedSwitchSignature) {
fprintf(gOutFile, "|%04x: packed-switch-data (%d units)", insnIdx, insnWidth);
} else if (instr == Instruction::kSparseSwitchSignature) {
fprintf(gOutFile, "|%04x: sparse-switch-data (%d units)", insnIdx, insnWidth);
} else if (instr == Instruction::kArrayDataSignature) {
fprintf(gOutFile, "|%04x: array-data (%d units)", insnIdx, insnWidth);
} else {
fprintf(gOutFile, "|%04x: nop // spacer", insnIdx);
}
} else {
fprintf(gOutFile, "|%04x: %s", insnIdx, pDecInsn->Name());
}
// Set up additional argument.
char indexBufChars[200];
char *indexBuf = indexBufChars;
if (Instruction::IndexTypeOf(pDecInsn->Opcode()) != Instruction::kIndexNone) {
indexBuf = indexString(pDexFile, pDecInsn,
indexBufChars, sizeof(indexBufChars));
}
// Dump the instruction.
//
// NOTE: pDecInsn->DumpString(pDexFile) differs too much from original.
//
switch (Instruction::FormatOf(pDecInsn->Opcode())) {
case Instruction::k10x: // op
break;
case Instruction::k12x: // op vA, vB
fprintf(gOutFile, " v%d, v%d", pDecInsn->VRegA(), pDecInsn->VRegB());
break;
case Instruction::k11n: // op vA, #+B
fprintf(gOutFile, " v%d, #int %d // #%x",
pDecInsn->VRegA(), (s4) pDecInsn->VRegB(), (u1)pDecInsn->VRegB());
break;
case Instruction::k11x: // op vAA
fprintf(gOutFile, " v%d", pDecInsn->VRegA());
break;
case Instruction::k10t: // op +AA
case Instruction::k20t: // op +AAAA
{
const s4 targ = (s4) pDecInsn->VRegA();
fprintf(gOutFile, " %04x // %c%04x",
insnIdx + targ,
(targ < 0) ? '-' : '+',
(targ < 0) ? -targ : targ);
}
break;
case Instruction::k22x: // op vAA, vBBBB
fprintf(gOutFile, " v%d, v%d", pDecInsn->VRegA(), pDecInsn->VRegB());
break;
case Instruction::k21t: // op vAA, +BBBB
{
const s4 targ = (s4) pDecInsn->VRegB();
fprintf(gOutFile, " v%d, %04x // %c%04x", pDecInsn->VRegA(),
insnIdx + targ,
(targ < 0) ? '-' : '+',
(targ < 0) ? -targ : targ);
}
break;
case Instruction::k21s: // op vAA, #+BBBB
fprintf(gOutFile, " v%d, #int %d // #%x",
pDecInsn->VRegA(), (s4) pDecInsn->VRegB(), (u2)pDecInsn->VRegB());
break;
case Instruction::k21h: // op vAA, #+BBBB0000[00000000]
// The printed format varies a bit based on the actual opcode.
if (pDecInsn->Opcode() == Instruction::CONST_HIGH16) {
const s4 value = pDecInsn->VRegB() << 16;
fprintf(gOutFile, " v%d, #int %d // #%x",
pDecInsn->VRegA(), value, (u2) pDecInsn->VRegB());
} else {
const s8 value = ((s8) pDecInsn->VRegB()) << 48;
fprintf(gOutFile, " v%d, #long %" PRId64 " // #%x",
pDecInsn->VRegA(), value, (u2) pDecInsn->VRegB());
}
break;
case Instruction::k21c: // op vAA, thing@BBBB
case Instruction::k31c: // op vAA, thing@BBBBBBBB
fprintf(gOutFile, " v%d, %s", pDecInsn->VRegA(), indexBuf);
break;
case Instruction::k23x: // op vAA, vBB, vCC
fprintf(gOutFile, " v%d, v%d, v%d",
pDecInsn->VRegA(), pDecInsn->VRegB(), pDecInsn->VRegC());
break;
case Instruction::k22b: // op vAA, vBB, #+CC
fprintf(gOutFile, " v%d, v%d, #int %d // #%02x",
pDecInsn->VRegA(), pDecInsn->VRegB(),
(s4) pDecInsn->VRegC(), (u1) pDecInsn->VRegC());
break;
case Instruction::k22t: // op vA, vB, +CCCC
{
const s4 targ = (s4) pDecInsn->VRegC();
fprintf(gOutFile, " v%d, v%d, %04x // %c%04x",
pDecInsn->VRegA(), pDecInsn->VRegB(),
insnIdx + targ,
(targ < 0) ? '-' : '+',
(targ < 0) ? -targ : targ);
}
break;
case Instruction::k22s: // op vA, vB, #+CCCC
fprintf(gOutFile, " v%d, v%d, #int %d // #%04x",
pDecInsn->VRegA(), pDecInsn->VRegB(),
(s4) pDecInsn->VRegC(), (u2) pDecInsn->VRegC());
break;
case Instruction::k22c: // op vA, vB, thing@CCCC
// NOT SUPPORTED:
// case Instruction::k22cs: // [opt] op vA, vB, field offset CCCC
fprintf(gOutFile, " v%d, v%d, %s",
pDecInsn->VRegA(), pDecInsn->VRegB(), indexBuf);
break;
case Instruction::k30t:
fprintf(gOutFile, " #%08x", pDecInsn->VRegA());
break;
case Instruction::k31i: // op vAA, #+BBBBBBBB
{
// This is often, but not always, a float.
union {
float f;
u4 i;
} conv;
conv.i = pDecInsn->VRegB();
fprintf(gOutFile, " v%d, #float %f // #%08x",
pDecInsn->VRegA(), conv.f, pDecInsn->VRegB());
}
break;
case Instruction::k31t: // op vAA, offset +BBBBBBBB
fprintf(gOutFile, " v%d, %08x // +%08x",
pDecInsn->VRegA(), insnIdx + pDecInsn->VRegB(), pDecInsn->VRegB());
break;
case Instruction::k32x: // op vAAAA, vBBBB
fprintf(gOutFile, " v%d, v%d", pDecInsn->VRegA(), pDecInsn->VRegB());
break;
case Instruction::k35c: // op {vC, vD, vE, vF, vG}, thing@BBBB
// NOT SUPPORTED:
// case Instruction::k35ms: // [opt] invoke-virtual+super
// case Instruction::k35mi: // [opt] inline invoke
{
u4 arg[Instruction::kMaxVarArgRegs];
pDecInsn->GetVarArgs(arg);
fputs(" {", gOutFile);
for (int i = 0, n = pDecInsn->VRegA(); i < n; i++) {
if (i == 0) {
fprintf(gOutFile, "v%d", arg[i]);
} else {
fprintf(gOutFile, ", v%d", arg[i]);
}
} // for
fprintf(gOutFile, "}, %s", indexBuf);
}
break;
case Instruction::k25x: // op vC, {vD, vE, vF, vG} (B: count)
{
u4 arg[Instruction::kMaxVarArgRegs25x];
pDecInsn->GetAllArgs25x(arg);
fprintf(gOutFile, " v%d, {", arg[0]);
for (int i = 0, n = pDecInsn->VRegB(); i < n; i++) {
if (i == 0) {
fprintf(gOutFile, "v%d", arg[Instruction::kLambdaVirtualRegisterWidth + i]);
} else {
fprintf(gOutFile, ", v%d", arg[Instruction::kLambdaVirtualRegisterWidth + i]);
}
} // for
fputc('}', gOutFile);
}
break;
case Instruction::k3rc: // op {vCCCC .. v(CCCC+AA-1)}, thing@BBBB
// NOT SUPPORTED:
// case Instruction::k3rms: // [opt] invoke-virtual+super/range
// case Instruction::k3rmi: // [opt] execute-inline/range
{
// This doesn't match the "dx" output when some of the args are
// 64-bit values -- dx only shows the first register.
fputs(" {", gOutFile);
for (int i = 0, n = pDecInsn->VRegA(); i < n; i++) {
if (i == 0) {
fprintf(gOutFile, "v%d", pDecInsn->VRegC() + i);
} else {
fprintf(gOutFile, ", v%d", pDecInsn->VRegC() + i);
}
} // for
fprintf(gOutFile, "}, %s", indexBuf);
}
break;
case Instruction::k51l: // op vAA, #+BBBBBBBBBBBBBBBB
{
// This is often, but not always, a double.
union {
double d;
u8 j;
} conv;
conv.j = pDecInsn->WideVRegB();
fprintf(gOutFile, " v%d, #double %f // #%016" PRIx64,
pDecInsn->VRegA(), conv.d, pDecInsn->WideVRegB());
}
break;
// NOT SUPPORTED:
// case Instruction::k00x: // unknown op or breakpoint
// break;
default:
fprintf(gOutFile, " ???");
break;
} // switch
fputc('\n', gOutFile);
if (indexBuf != indexBufChars) {
free(indexBuf);
}
}