A temporal dependency occurs when developers change two or more files at the same time (i.e. they are a part of the same commit).
Pairs | # same commits | # commits 1 | # commits 2 | latest commit |
---|---|---|---|---|
fpga-region.c altera-freeze-bridge.c |
3 | 143 (2%) | 65 (4%) | 2022-01-15 |
xilinx-spi.c of-fpga-region.c |
3 | 144 (2%) | 93 (3%) | 2022-01-15 |
zynqmp-fpga.c ts73xx-fpga.c |
3 | 92 (3%) | 108 (2%) | 2022-01-15 |
xilinx-spi.c altera-pr-ip-core.c |
3 | 144 (2%) | 74 (4%) | 2022-01-15 |
ts73xx-fpga.c ice40-spi.c |
3 | 108 (2%) | 125 (2%) | 2022-01-15 |
fpga-region.c fpga-mgr.c |
3 | 143 (2%) | 215 (1%) | 2022-01-15 |
zynqmp-fpga.c machxo2-spi.c |
3 | 92 (3%) | 99 (3%) | 2022-01-15 |
dfl.c altera-freeze-bridge.c |
3 | 193 (1%) | 65 (4%) | 2022-01-15 |
ice40-spi.c dfl.c |
3 | 125 (2%) | 193 (1%) | 2022-01-15 |
machxo2-spi.c dfl-fme-mgr.c |
3 | 99 (3%) | 72 (4%) | 2022-01-15 |
xilinx-pr-decoupler.c dfl-fme-mgr.c |
3 | 129 (2%) | 72 (4%) | 2022-01-15 |
machxo2-spi.c dfl.c |
3 | 99 (3%) | 193 (1%) | 2022-01-15 |
xilinx-pr-decoupler.c dfl.c |
3 | 129 (2%) | 193 (1%) | 2022-01-15 |
versal-fpga.c dfl.c |
3 | 15 (20%) | 193 (1%) | 2022-01-15 |
fpga-region.c altera-cvp.c |
3 | 143 (2%) | 193 (1%) | 2022-01-15 |
machxo2-spi.c altera-freeze-bridge.c |
3 | 99 (3%) | 65 (4%) | 2022-01-15 |
xilinx-pr-decoupler.c altera-pr-ip-core.c |
3 | 129 (2%) | 74 (4%) | 2022-01-15 |
fpga-mgr.c altera-pr-ip-core.c |
3 | 215 (1%) | 74 (4%) | 2022-01-15 |
zynq-fpga.c dfl-fme-mgr.c |
3 | 189 (1%) | 72 (4%) | 2022-01-15 |
zynq-fpga.c altera-cvp.c |
3 | 189 (1%) | 193 (1%) | 2022-01-15 |
stratix10-soc.c dfl.c |
3 | 134 (2%) | 193 (1%) | 2022-01-15 |
fpga-mgr.c dfl-fme-mgr.c |
3 | 215 (1%) | 72 (4%) | 2022-01-15 |
of-fpga-region.c machxo2-spi.c |
3 | 93 (3%) | 99 (3%) | 2022-01-15 |
ts73xx-fpga.c fpga-mgr.c |
3 | 108 (2%) | 215 (1%) | 2022-01-15 |
ts73xx-fpga.c of-fpga-region.c |
3 | 108 (2%) | 93 (3%) | 2022-01-15 |
stratix10-soc.c altera-freeze-bridge.c |
3 | 134 (2%) | 65 (4%) | 2022-01-15 |
zynqmp-fpga.c altera-freeze-bridge.c |
3 | 92 (3%) | 65 (4%) | 2022-01-15 |
zynqmp-fpga.c altera-pr-ip-core.c |
3 | 92 (3%) | 74 (4%) | 2022-01-15 |
fpga-mgr.c altera-freeze-bridge.c |
3 | 215 (1%) | 65 (4%) | 2022-01-15 |
xilinx-spi.c dfl.c |
3 | 144 (2%) | 193 (1%) | 2022-01-15 |
zynq-fpga.c fpga-region.c |
3 | 189 (1%) | 143 (2%) | 2022-01-15 |
xilinx-spi.c machxo2-spi.c |
3 | 144 (2%) | 99 (3%) | 2022-01-15 |
fpga-region.c fpga-bridge.c |
3 | 143 (2%) | 151 (1%) | 2022-01-15 |
xilinx-pr-decoupler.c ts73xx-fpga.c |
3 | 129 (2%) | 108 (2%) | 2022-01-15 |
of-fpga-region.c altera-pr-ip-core.c |
3 | 93 (3%) | 74 (4%) | 2022-01-15 |
versal-fpga.c machxo2-spi.c |
3 | 15 (20%) | 99 (3%) | 2022-01-15 |
fpga-region.c altera-pr-ip-core.c |
3 | 143 (2%) | 74 (4%) | 2022-01-15 |
ts73xx-fpga.c machxo2-spi.c |
3 | 108 (2%) | 99 (3%) | 2022-01-15 |
zynq-fpga.c of-fpga-region.c |
3 | 189 (1%) | 93 (3%) | 2022-01-15 |
stratix10-soc.c altera-cvp.c |
3 | 134 (2%) | 193 (1%) | 2022-01-15 |
ice40-spi.c fpga-mgr.c |
3 | 125 (2%) | 215 (1%) | 2022-01-15 |
xilinx-pr-decoupler.c stratix10-soc.c |
3 | 129 (2%) | 134 (2%) | 2022-01-15 |
stratix10-soc.c machxo2-spi.c |
3 | 134 (2%) | 99 (3%) | 2022-01-15 |
stratix10-soc.c ice40-spi.c |
3 | 134 (2%) | 125 (2%) | 2022-01-15 |
zynqmp-fpga.c of-fpga-region.c |
3 | 92 (3%) | 93 (3%) | 2022-01-15 |
ts73xx-fpga.c altera-freeze-bridge.c |
3 | 108 (2%) | 65 (4%) | 2022-01-15 |
ts73xx-fpga.c fpga-bridge.c |
3 | 108 (2%) | 151 (1%) | 2022-01-15 |
versal-fpga.c stratix10-soc.c |
3 | 15 (20%) | 134 (2%) | 2022-01-15 |
xilinx-spi.c fpga-bridge.c |
3 | 144 (2%) | 151 (1%) | 2022-01-15 |
stratix10-soc.c fpga-region.c |
3 | 134 (2%) | 143 (2%) | 2022-01-15 |